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ngLatencyCyclesUrgentOutOfOrderReturnPerChannelUrgentOutOfOrderReturnPerChannelPixelDataOnlyUrgentOutOfOrderReturnPerChannelPixelMixedWithVMDataUrgentOutOfOrderReturnPerChannelVMDataOnlyVMMPageSizeXFCBusTransportTimeUseUrgentBurstBandwidthXFCXBUFLatencyToleranceROBBufferSizeInKByteDETBufferSizeInKByteDETBufferSizeInTimeDPPOutputBufferPixelsOPPOutputBufferLinesPixelChunkSizeInKByteReturnBWGPUVMEnableHostVMEnableGPUVMMaxPageTableLevelsHostVMMaxPageTableLevelsHostVMCachedPageTableLevelsOverrideGPUVMPageTableLevelsOverrideHostVMPageTableLevelsMetaChunkSizeMinMetaChunkSizeBytesWritebackChunkSizeODMCapabilityNumberOfDSCLineBufferSizeMaxLineBufferLinesWritebackInterfaceLumaBufferSizeWritebackInterfaceChromaBufferSizeWritebackChromaLineBufferWidthWritebackConfigurationMaxDCHUBToPSCLThroughputMaxPSCLToLBThroughputPTEBufferSizeInRequestsLumaPTEBufferSizeInRequestsChromaDISPCLKRampingMarginMaxInterDCNTileRepeatersXFCSupportedXFCSlvChunkSizeXFCFillBWOverheadXFCFillConstantXFCTSlvVupdateOffsetXFCTSlvVupdateWidthXFCTSlvVreadyOffsetDPPCLKDelaySubtotalDPPCLKDelaySCLDPPCLKDelaySCLLBOnlyDPPCLKDelayCNVCFormaterDPPCLKDelayCNVCCursorDISPCLKDelaySubtotalCompressedBufferSegmentSizeInkByteFinalCompbufReservedSpace64BCompbufReservedSpaceZsLineBufferSizeFinalMaximumPixelsPerLinePerDSCUnitAlphaPixelChunkSizeInKByteMinPixelChunkSizeBytesDCCMetaBufferSizeBytesVoltageLevelFabricClockDRAMSpeedDISPCLKSOCCLKDCFCLKMaxTotalDETInKByteMinCompressedBufferSizeInKByteNumberOfActiveSurfacesRefreshRateOutputBPPGPUVMMinPageSizeKBytesSynchronizeTimingsFinalSynchronizeDRRDisplaysForUCLKPStateChangeFinalForceOneRowForFrameViewportXStartYDRRDisplayPteBufferModeOutputTypeOutputRateNumberOfActivePlanesNumberOfDSCSlicesViewportWidthViewportYStartYHRatioHTAPsChromaVTAPsChromaVTotalVTotal_MaxVTotal_MinDPPPerPlanePixelClockBackEndFECEnableSourceScanWritebackEnableActiveWritebacksPerPlaneWritebackDestinationWidthWritebackDestinationHeightWritebackSourceHeightWritebackPixelFormatWritebackLumaHTapsWritebackLumaVTapsWritebackChromaHTapsWritebackChromaVTapsWritebackHRatioWritebackVRatioVActiveScalerRecoutWidthDynamicMetadataEnableDynamicMetadataLinesBeforeActiveRequiredDynamicMetadataTransmittedBytesDCCRateAverageDCCCompressionRateODMCombineEnabledOutputBppDSCEnabledDSCInputBitPerComponentOutputFormatOutputskip_dio_checkBlendingAndTimingSynchronizedVBlankCursorWidthCursorBPPXFCEnabledVBlankNomDisableUnboundRequestIfCompBufReservedSpaceNeedAdjustmentImmediateFlipSupportDETBufferSizeYDETBufferSizeCLBBitPerPixelLastPixelOfLineExtraWatermarkTotalDataReadBandwidthTotalActiveWritebackEffectiveLBLatencyHidingSourceLinesLumaEffectiveLBLatencyHidingSourceLinesChromaBandwidthAvailableForImmediateFlipPrefetchModePrefetchModePerStateMinPrefetchModeMaxPrefetchModeAnyLinesForVMOrRowTooLargeMaxVStartupIgnoreViewportPositioningErrorResultDCFCLKDeepSleepUrgentExtraLatencyStutterEfficiencyStutterEfficiencyNotIncludingVBlankNonUrgentLatencyToleranceMinActiveDRAMClockChangeLatencySupportedZ8StutterEfficiencyBestCaseZ8NumberOfStutterBurstsPerFrameBestCaseZ8StutterEfficiencyNotIncludingVBlankBestCaseStutterPeriodBestCaseWatermarkDCHUBBUB_ARB_CSTATE_MAX_CAP_MODECompBufReservedSpaceKBytesCompBufReservedSpace64BCompBufReservedSpaceZsCompBufReservedSpaceNeedAdjustmentDISPCLK_calculatedDPPCLK_calculatedImmediateFlipSupportedSurfaceUse_One_Row_For_FrameUse_One_Row_For_Frame_FlipVUpdateOffsetPixVUpdateWidthPixVReadyOffsetPixTotImmediateFlipBytesTCalccache_pipescache_num_pipespipe_planeSupportGFX7CompatibleTilingIn32bppAnd64bppMaxHSCLRatioMaxVSCLRatioMaxNumWritebackWritebackLumaAndChromaScalingSupportedCursor64BppSupportDCFCLKPerStateDCFCLKStateFabricClockPerStateSOCCLKPerStatePHYCLKPerStateDTBCLKPerStateMaxDppclkMaxDSCCLKDRAMSpeedPerStateMaxDispclkVoltageOverrideLevelPHYCLKD32PerStateScaleRatioAndTapsSupportSourceFormatPixelAndScanSupportTotalBandwidthConsumedGBytePerSecondDCCEnabledInAnyPlaneWritebackLatencySupportWritebackModeSupportWriteback10bpc420SupportedBandwidthSupportTotalNumberOfActiveWritebackCriticalPointReturnBWToDCNPerStateIsErrorResultprefetch_vm_bw_validprefetch_row_bw_validNumberOfOTGSupportNonsupportedDSCInputBPCWritebackScaleRatioAndTapsSupportCursorSupportPitchSupportValidationStatusP2IWith420DSCOnlyIfNecessaryWithBPPDSC422NativeNotSupportedLinkRateDoesNotMatchDPVersionLinkRateForMultistreamNotIndicatedBPPForMultistreamNotIndicatedMultistreamWithHDMIOreDPMSOOrODMSplitWithNonDPLinkNotEnoughLanesForMSOViewportExceedsSurfaceImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecifiedImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipeInvalidCombinationOfMALLUseForPStateAndStaticScreenInvalidCombinationOfMALLUseForPStateOutputLinkDPRatePrefetchLinesYThisStatePrefetchLinesCThisStatemeta_row_bandwidth_this_statedpte_row_bandwidth_this_stateDPTEBytesPerRowThisStatePDEAndMetaPTEBytesPerFrameThisStateMetaRowBytesThisStateuse_one_row_for_frameuse_one_row_for_frame_flipuse_one_row_for_frame_this_stateuse_one_row_for_frame_flip_this_stateOutputTypeAndRatePerStateRequiredDISPCLKPerSurfaceMacroTileHeightYMacroTileHeightCMacroTileWidthYMacroTileWidthCImmediateFlipRequiredFinalDCCProgrammingAssumesScanDirectionUnknownFinalEnoughWritebackUnitsODMCombine2To1SupportCheckOKNumberOfDP2p0SupportMaxNumDP2p0StreamsMaxNumDP2p0OutputsOutputTypePerStateOutputRatePerStateWritebackLineBufferLumaBufferSizeWritebackLineBufferChromaBufferSizeWritebackMinHSCLRatioWritebackMinVSCLRatioWritebackMaxHSCLRatioWritebackMaxVSCLRatioWritebackMaxHSCLTapsWritebackMaxVSCLTapsMaxNumDPPMaxNumOTGCursorBufferSizeCursorChunkSizeModeOutputLinkDPLanesForcedOutputLinkBPPImmediateFlipBWMaxMaxVStartupWritebackLumaVExtraWritebackChromaVExtraWritebackRequiredDISPCLKMaximumSwathWidthSupportMaximumSwathWidthInDETBufferMaximumSwathWidthInLineBufferMaxDispclkRoundedDownToDFSGranularityMaxDppclkRoundedDownToDFSGranularityPlaneRequiredDISPCLKWithoutODMCombinePlaneRequiredDISPCLKWithODMCombinePlaneRequiredDISPCLKFECOverheadEffectiveFECOverheadOutbppOutbppDSCslicesSwathWidthGranularityYRoundedUpMaxSwathSizeBytesYSwathWidthGranularityCRoundedUpMaxSwathSizeBytesCEffectiveDETLBLinesLumaEffectiveDETLBLinesChromaProjectedDCFCLKDeepSleepPDEAndMetaPTEBytesPerFrameYPDEAndMetaPTEBytesPerFrameCMetaRowBytesYMetaRowBytesCDPTEBytesPerRowCDPTEBytesPerRowYTimeCalcTWaitMaximumReadBandwidthWithPrefetchMaximumReadBandwidthWithoutPrefetchtotal_dcn_read_bw_with_fliptotal_dcn_read_bw_with_flip_no_urgent_burstFractionOfUrgentBandwidthFractionOfUrgentBandwidthImmediateFlipIdealSDPPortBandwidthPerStateNoOfDPPNoOfDPPThisStateODMCombineEnablePerStateSwathWidthYThisStateSwathHeightCPerStateSwathHeightYThisStateSwathHeightCThisStateVRatioPreYVRatioPreCRequiredPrefetchPixelDataBWLumaRequiredPrefetchPixelDataBWChromaRequiredDPPCLKRequiredDPPCLKThisStatePTEBufferSizeNotExceededYPTEBufferSizeNotExceededCBandwidthWithoutPrefetchSupportedPrefetchSupportedVRatioInPrefetchSupportedRequiredDISPCLKDISPCLK_DPPCLK_SupportTotalAvailablePipesSupportTotalNumberOfActiveDPPTotalNumberOfDCCActiveDPPModeSupportReturnBWPerStateDIOSupportNotEnoughDSCUnitsDSCCLKRequiredMoreThanSupportedDTBCLKRequiredMoreThanSupportedUrgentRoundTripAndOutOfOrderLatencyPerStateROBSupportDCCMetaBufferSizeSupportPTEBufferSizeNotExceededTotalVerticalActiveBandwidthSupportMaxTotalVerticalActiveAvailableBandwidthPrefetchBWPDEAndMetaPTEBytesPerFrameMetaRowBytesDPTEBytesPerRowPrefetchLinesYPrefetchLinesCMaxNumSwYMaxNumSwCPrefillYPrefillCLineTimesForPrefetchLinesForMetaPTELinesForMetaAndDPTERowMinDPPCLKUsingSingleDPPSwathWidthYSingleDPPBytePerPixelInDETYBytePerPixelInDETCRequiresDSCNumberOfDSCSliceRequiresFECOutputBppPerStateDSCDelayPerStateViewportSizeSupportRead256BlockHeightYRead256BlockWidthYRead256BlockHeightCRead256BlockWidthCMaxSwathHeightYMaxSwathHeightCMinSwathHeightYMinSwathHeightCReadBandwidthLumaReadBandwidthChromaReadBandwidthWriteBandwidthPSCL_FACTORPSCL_FACTOR_CHROMAMaximumVStartupAlignedDCCMetaPitchAlignedYPitchAlignedCPitchMaximumSwathWidthcursor_bwcursor_bw_preTno_bwprefetch_vmrow_bwDestinationLinesToRequestVMInImmediateFlipDestinationLinesToRequestRowInImmediateFlipfinal_flip_bwImmediateFlipSupportedForStateWritebackDelayvm_group_bytesmeta_req_heightmeta_req_widthmeta_row_widthdpte_row_height_chromameta_req_height_chromameta_req_width_chromameta_row_height_chromameta_row_width_chromaImmediateFlipSupportedForPipemeta_row_bwdpte_row_bwDisplayPipeLineDeliveryTimeLumaDisplayPipeLineDeliveryTimeChromaDisplayPipeRequestDeliveryTimeLumaDisplayPipeRequestDeliveryTimeChromaDRAMClockChangeSupportUrgentBurstFactorCursorUrgentBurstFactorCursorPreUrgentBurstFactorLumaUrgentBurstFactorLumaPreUrgentBurstFactorChromaUrgentBurstFactorChromaPreMPCCombineSwathWidthCSingleDPPMaximumSwathWidthInLineBufferLumaMaximumSwathWidthInLineBufferChromaMaximumSwathWidthLumaMaximumSwathWidthChromaodm_combine_dummydummy5dummy6dummy7dummy8dummy13dummyinteger3dummyinteger4dummyinteger5dummyinteger6dummyinteger7dummyinteger8dummyinteger9dummyinteger10dummyinteger11dummysinglestringSingleDPPViewportSizeSupportPerPlanePlaneRequiredDISPCLKWithODMCombine2To1PlaneRequiredDISPCLKWithODMCombine4To1TotalNumberOfSingleDPPPlanesLinkDSCEnableODMCombine4To1SupportCheckOKODMCombineEnableThisStateSwathWidthCThisStateViewportSizeSupportPerPlaneAlignedDCCMetaPitchYAlignedDCCMetaPitchCNotEnoughUrgentLatencyHidingNotEnoughUrgentLatencyHidingPrePTEBufferSizeInRequestsForLumaPTEBufferSizeInRequestsForChromadpte_group_bytes_chromavm_group_bytes_chromadst_x_after_scalerVStartupRequiredWhenNotEnoughTimeForDynamicMetadataPrefetchBandwidthVInitPreFillYVInitPreFillCMaxNumSwathYMaxNumSwathCVStartupAllowDRAMClockChangeDuringVBlankAllowDRAMSelfRefreshDuringVBlankVRatioPrefetchYVRatioPrefetchCDestinationLinesForPrefetchDestinationLinesToRequestVMInVBlankDestinationLinesToRequestRowInVBlankMinTTUVBlankBytePerPixelDETYBytePerPixelDETCSwathWidthYSwathWidthSingleDPPYCursorRequestDeliveryTimeCursorRequestDeliveryTimePrefetchReadBandwidthPlaneLumaReadBandwidthPlaneChromaDisplayPipeLineDeliveryTimeLumaPrefetchDisplayPipeLineDeliveryTimeChromaPrefetchDisplayPipeRequestDeliveryTimeLumaPrefetchDisplayPipeRequestDeliveryTimeChromaPrefetchPixelPTEBytesPerRowPDEAndMetaPTEBytesFrameMetaRowBytePrefetchSourceLinesYRequiredPrefetchPixDataBWLumaRequiredPrefetchPixDataBWChromaPrefetchSourceLinesCPSCL_THROUGHPUT_LUMAPSCL_THROUGHPUT_CHROMADSCCLK_calculatedDSCDelayMaxVStartupLinesDPPCLKUsingSingleDPPDPPCLKDCCYMaxUncompressedBlockDCCYMaxCompressedBlockDCCYIndependent64ByteBlockMaximumDCCCompressionYSurfaceXFCSlaveVUpdateOffsetXFCSlaveVupdateWidthXFCSlaveVReadyOffsetXFCTransferDelayXFCPrechargeDelayXFCRemoteSurfaceFlipLatencyXFCPrefetchMargindpte_row_width_luma_ubdpte_row_width_chroma_ubFullDETBufferingTimeYFullDETBufferingTimeCDST_Y_PER_PTE_ROW_NOM_LDST_Y_PER_PTE_ROW_NOM_CDST_Y_PER_META_ROW_NOM_LTimePerMetaChunkNominalTimePerMetaChunkVBlankTimePerMetaChunkFlipswath_width_luma_ubswath_width_chroma_ubPixelPTEReqWidthYPixelPTEReqHeightYPTERequestSizeYPixelPTEReqWidthCPixelPTEReqHeightCPTERequestSizeCtime_per_pte_group_nom_lumatime_per_pte_group_nom_chromatime_per_pte_group_vblank_lumatime_per_pte_group_vblank_chromatime_per_pte_group_flip_lumatime_per_pte_group_flip_chromaTimePerVMGroupVBlankTimePerVMGroupFlipTimePerVMRequestVBlankTimePerVMRequestFlipdpde0_bytes_per_frame_ub_lmeta_pte_bytes_per_frame_ub_ldpde0_bytes_per_frame_ub_cmeta_pte_bytes_per_frame_ub_cLinesToFinishSwathTransferStutterCriticalPlaneBytePerPixelYCriticalPlaneSwathWidthYCriticalPlaneLinesInDETYLinesInDETYRoundedDownToSwathSwathWidthSingleDPPCSwathWidthCdummyinteger1dummyinteger2FinalDRAMClockChangeLatencyTdmdl_vmTdmdlTSetupThisVStartupWritebackAllowDRAMClockChangeEndPositionDST_Y_PER_META_ROW_NOM_CTimePerChromaMetaChunkNominalTimePerChromaMetaChunkVBlankTimePerChromaMetaChunkFlipDCCCMaxUncompressedBlockDCCCMaxCompressedBlockVStartupMarginNotEnoughTimeForDynamicMetadataMaximumMaxVStartupLinesFabricAndDRAMBandwidthLinesInDETLumaLinesInDETChromaImmediateFlipBytesLinesInDETCLinesInDETCRoundedDownToSwathUrgentLatencySupportUsPerStateUrgentLatencySupportUsFabricAndDRAMBandwidthPerStateUrgentLatencySupportSwathWidthYPerStateSwathHeightYPerStatequal_row_bwprefetch_row_bwprefetch_vm_bwPTEGroupSizePDEProcessingBufIn64KBReqsDoUrgentLatencyAdjustmentUrgentLatencyAdjustmentFabricClockComponentUrgentLatencyAdjustmentFabricClockReferenceMinUrgentLatencySupportUsMinFullDETBufferingTimeAverageReadBandwidthGBytePerSecondFirstMainPlaneNotEnoughDETSwathFillLatencyHidingViewportWidthChromaHRatioChromaWritebackSourceWidthModeIsSupportedODMCombine4To1SupportedSurfaceWidthYSurfaceWidthCSurfaceHeightYSurfaceHeightCWritebackHTapsWritebackVTapsDSCEnableDRAMClockChangeLatencyOverrideGPUVMMinPageSizeHostVMMinPageSizeMPCCombineEnableHostVMMaxNonCachedPageTableLevelsDynamicMetadataVMEnabledWritebackInterfaceBufferSizeWritebackLineBufferSizeDCCRateLumaDCCRateChromaPHYCLKD18PerStateWritebackSupportInterleaveAndUsingWholeBufferForASingleStreamNumberOfHDMIFRLSupportMaxNumHDMIFRLOutputsAudioSampleRateAudioSampleLayoutPercentMarginOverMinimumRequiredDCFCLKDynamicMetadataSupportedImmediateFlipRequirementDETBufferSizeYThisStateDETBufferSizeCThisStateNoUrgentLatencyHidingNoUrgentLatencyHidingPreswath_width_luma_ub_this_stateswath_width_chroma_ub_this_stateUrgLatencyVActiveCursorBandwidthVActivePixelBandwidthNoTimeForPrefetchNoTimeForDynamicMetadatadpte_row_bandwidthmeta_row_bandwidthDETBufferSizeYAllStatesDETBufferSizeCAllStatesswath_width_luma_ub_all_statesswath_width_chroma_ub_all_statesNotUrgentLatencyHidingSwathHeightYAllStatesSwathHeightCAllStatesSwathWidthYAllStatesSwathWidthCAllStatesTotalDPTERowBandwidthTotalMetaRowBandwidthTotalVActiveCursorBandwidthTotalVActivePixelBandwidthWritebackDelayTimeDCCYIndependentBlockDCCCIndependentBlockdummyinteger17dummyinteger18dummyinteger19dummyinteger20dummyinteger21dummyinteger22dummyinteger23dummyinteger24dummyinteger25dummyinteger26dummyinteger27dummyinteger28dummyinteger29dummystringBPPODMCombinePolicyUseMinimumRequiredDCFCLKClampMinDCFCLKAllowDramClockChangeOneDisplayVactiveMaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperationPercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatencyPercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelMixedWithVMDataPercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnlyPercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelDataOnlyZ8StutterEfficiencyNotIncludingVBlankZ8StutterEfficiencyDCCFractionOfZeroSizeRequestsLumaDCCFractionOfZeroSizeRequestsChromaUrgBurstFactorCursorUrgBurstFactorLumaUrgBurstFactorChromaUrgBurstFactorCursorPreUrgBurstFactorLumaPreUrgBurstFactorChromaPreNotUrgentLatencyHidingPreLinkCapacitySupportVREADY_AT_OR_AFTER_VSYNCMIN_DST_Y_NEXT_STARTVFrontPorchConfigReturnBufferSizeInKByteUseUnboundedRequestingCompressedBufferSegmentSizeInkByteCompressedBufferSizeInkByteMetaFIFOSizeInKEntriesZeroSizeBufferEntriesCOMPBUF_RESERVED_SPACE_64BCOMPBUF_RESERVED_SPACE_ZSUnboundedRequestEnabledDSC422NativeSupportNoEnoughUrgentLatencyHidingNoEnoughUrgentLatencyHidingPreNumberOfStutterBurstsPerFrameZ8NumberOfStutterBurstsPerFrameMaximumDSCBitsPerComponentNotEnoughUrgentLatencyHidingAReadBandwidthSurfaceLumaReadBandwidthSurfaceChromaSurfaceRequiredDISPCLKWithoutODMCombineSurfaceRequiredDISPCLKMinActiveFCLKChangeLatencySupportedMinVoltageLevelMaxVoltageLevelTotalNumberOfSingleDPPSurfacesCompressedBufferSizeInkByteAllStatesDETBufferSizeInKByteAllStatesDETBufferSizeInKByteThisStateSurfaceSizeInMALLExceededMALLSizePTE_BUFFER_MODEBIGK_FRAGMENT_SIZECompressedBufferSizeInkByteThisStateFCLKChangeSupportUSRRetrainingSupportUsesMALLForPStateChangeUnboundedRequestEnabledAllStatesSingleDPPViewportSizeSupportPerSurfaceUseMALLForStaticScreenUnboundedRequestEnabledThisStateDRAMClockChangeRequirementFinalFCLKChangeRequirementFinalUSRRetrainingRequiredFinalDETSizeOverridenomDETInKByteMPCCombineUseMPCCombineMethodIncompatibleRequiredSlotsExceededMultistreamSlotsODMUseOutputMultistreamIdOutputMultistreamEnUsesMALLForStaticScreenMaxActiveDRAMClockChangeLatencySupportedWritebackAllowFCLKChangeEndPositionPTEBufferSizeNotExceededPerStateDCCMetaBufferSizeNotExceededPerStateNotEnoughDSCSlicesPixelsPerLinePerDSCUnitSupportDCCMetaBufferSizeNotExceededdpte_row_height_lineardpte_row_height_linear_chromaSubViewportLinesNeededInMALLVActiveBandwithSupportNotEnoughDETSwathFillLatencyHidingPerStatedml_projectDML_PROJECT_UNDEFINEDDML_PROJECT_RAVEN1DML_PROJECT_NAVI10DML_PROJECT_NAVI10v2DML_PROJECT_DCN201DML_PROJECT_DCN21DML_PROJECT_DCN30DML_PROJECT_DCN31DML_PROJECT_DCN315DML_PROJECT_DCN314DML_PROJECT_DCN32dml_funcsrq_dlg_get_dlg_regrq_dlg_get_rq_regrq_dlg_get_dlg_reg_v2rq_dlg_get_rq_reg_v2display_mode_libprojectvbadml_pipe_statevalidate_max_statedml2_soc_mall_infocache_line_size_bytescache_num_waysmax_cab_allocation_bytesmblk_width_pixelsmblk_size_bytesmblk_height_4bpe_pixelsmblk_height_8bpe_pixelsdml2_dc_callbacksbuild_scaling_paramscan_support_mclk_switch_using_fw_based_vblank_stretchacquire_secondary_pipe_for_mpc_odmupdate_pipes_for_stream_with_slice_countupdate_pipes_for_plane_with_slice_countget_odm_slice_indexget_mpc_slice_indexget_opp_headdml2_dc_svp_callbackscreate_phantom_streamcreate_phantom_planeadd_phantom_streamadd_phantom_planeremove_phantom_planeremove_phantom_streamrelease_phantom_planerelease_phantom_streamrelease_dscget_pipe_subvp_typeget_stream_subvp_typeget_paired_subvp_streamresource_contextis_stream_enc_acquiredis_audio_acquiredclock_source_ref_countdp_clock_source_ref_countis_dsc_acquiredlink_enc_cfg_ctxis_hpo_dp_stream_enc_acquiredhpo_dp_link_enc_to_link_idxhpo_dp_link_enc_ref_cntsis_mpc_3dlut_acquiredtemp_pipedisplay_stream_compressordml2_clks_table_entryfclk_mhzmemclk_mhzdml2_clks_num_entriesnum_dcfclk_levelsnum_fclk_levelsnum_memclk_levelsnum_socclk_levelsnum_dtbclk_levelsnum_dispclk_levelsnum_dppclk_levelsdml2_clks_limit_tableclk_entriesnum_entries_per_clkdml2_soc_bbox_overridesxtalclk_mhzdchub_refclk_mhzdprefclk_mhzdisp_pll_vco_speed_mhzsr_exit_latency_ussr_enter_plus_exit_latency_usdram_num_chandram_chanel_width_bytesclks_tableforce_disable_subvpforce_enable_subvpsubvp_fw_processing_delay_ussubvp_pstate_allow_width_ussubvp_prefetch_end_to_mall_start_ussubvp_swath_height_margin_linesdml2_configuration_optionsdcn_pipe_countuse_native_pstate_optimizationenable_windowed_mpo_odmuse_native_soc_bb_constructionskip_hw_state_mappingoptimize_odm_4to1minimize_dispclk_using_odmoverride_det_buffer_size_kbytessvp_pstatemall_cfgbbox_overridesmax_segments_per_hubpdet_segment_sizemap_dc_pipes_with_callbacksdc_versionsdc_verdp_protocol_versionDP_VERSION_1_4DP_VERSION_2_1DP_VERSION_UNKNOWNdc_plane_typeDC_PLANE_TYPE_INVALIDDC_PLANE_TYPE_DCE_RGBDC_PLANE_TYPE_DCE_UNDERLAYDC_PLANE_TYPE_DCN_UNIVERSALdet_sizeDET_SIZE_DEFAULTDET_SIZE_192KBDET_SIZE_256KBDET_SIZE_320KBDET_SIZE_384KBargb8888nv12fp16p010ayuvdc_plane_cappixel_format_supportmax_upscale_factormax_downscale_factorrom_curve_capssrgbbt2020gamma2_2hlgdpp_color_capsdcn_archinput_lut_sharedicscdgam_rampost_cscgamma_corrhw_3d_lutogam_ramocscdgam_rom_for_yuvdgam_rom_capsogam_rom_capsmpc_color_capsgamut_remapnum_3dlutsshared_3d_lutdc_color_capsdppdc_dmub_capsmclk_swsubvp_psrgecc_enabledc_capsmax_linksmax_audiosmax_slave_planesmax_slave_yuv_planesmax_slave_rgb_planesmax_planesmax_downscale_ratioi2c_speed_in_khzi2c_speed_in_khz_hdcpdmdata_alloc_sizemax_cursor_sizemax_video_widthmax_optimizable_video_widthmin_horizontal_blanking_periodlinear_pitch_alignmentdynamic_audiodual_link_dvipost_blend_color_processingforce_dp_tps4_for_cp2520disable_dp_clk_sharepsp_setup_panel_modeextended_aux_timeout_supportdmcub_supportzstate_supportips_supportnum_of_internal_dispmax_dp_protocol_versionmall_size_per_mem_channelmall_size_totalcursor_cache_sizedmub_capsdp_hpodp_hdmi21_pcon_supportedp_dsc_supportvbios_lttpr_awarevbios_lttpr_enablemax_otg_numsubvp_drr_max_vblank_margin_ussubvp_vertical_int_margin_usseamless_odmmax_v_totalmax_disp_clock_khz_at_vminsubvp_drr_vblank_start_margin_usdcfclkdcfclk_dsdc_bug_wano_connect_phy_configdedcn20_305_waskip_clock_updatelt_early_cr_patternclock_update_disable_maskdc_dcc_surface_paramswizzle_modedcc_256_64_64dcc_128_1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AUDIO_DTO1_PHASEAUDIO_RATE_CAPABILITIESdce_audio_shiftAZALIA_ENDPOINT_REG_INDEXAZALIA_ENDPOINT_REG_DATACLKSTOPEPSSDCCG_AUDIO_DTO0_SOURCE_SELDCCG_AUDIO_DTO_SELDCCG_AUDIO_DTO2_USE_512FBR_DTODCCG_AUDIO_DTO0_USE_512FBR_DTODCCG_AUDIO_DTO1_USE_512FBR_DTOCLOCK_GATING_DISABLEdce_audio_maskdce_panel_cntl_shiftLVTMA_BLONLVTMA_BLON_OVRDLVTMA_DIGONLVTMA_DIGON_OVRDLVTMA_PWRSEQ_TARGET_STATELVTMA_PWRSEQ_TARGET_STATE_RBL_PWM_REF_DIVBL_PWM_ENBL_ACTIVE_INT_FRAC_CNTBL_PWM_FRACTIONAL_ENBL_PWM_PERIODBL_PWM_PERIOD_BITCNTBL_PWM_GRP1_IGNORE_MASTER_LOCK_ENBL_PWM_GRP1_REG_LOCKBL_PWM_GRP1_REG_UPDATE_PENDINGdce_panel_cntl_maskdce_panel_cntl_registersPWRSEQ_CNTLPWRSEQ_STATEPWRSEQ_REF_DIVBIOS_SCRATCH_2dce_panel_cntli2caux_transaction_operationI2CAUX_TRANSACTION_READI2CAUX_TRANSACTION_WRITEi2caux_transaction_address_spaceI2CAUX_TRANSACTION_ADDRESS_SPACE_I2CI2CAUX_TRANSACTION_ADDRESS_SPACE_DPCDi2caux_transaction_payloadi2caux_transaction_statusI2CAUX_TRANSACTION_STATUS_UNKNOWNI2CAUX_TRANSACTION_STATUS_SUCCEEDEDI2CAUX_TRANSACTION_STATUS_FAILED_CHANNEL_BUSYI2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUTI2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERRORI2CAUX_TRANSACTION_STATUS_FAILED_NACKI2CAUX_TRANSACTION_STATUS_FAILED_INCOMPLETEI2CAUX_TRANSACTION_STATUS_FAILED_OPERATIONI2CAUX_TRANSACTION_STATUS_FAILED_INVALID_OPERATIONI2CAUX_TRANSACTION_STATUS_FAILED_BUFFER_OVERFLOWI2CAUX_TRANSACTION_STATUS_FAILED_HPD_DISCONi2caux_transaction_requestALLOW_AUX_WHEN_HPD_LOWaux_configaux_engineaux_engine_funcsconfigure_timeoutacquire_enginesubmit_channel_requestprocess_channel_replyread_channel_replyget_channel_statusis_engine_availablesubmit_requestrelease_enginedestroy_enginedce110_aux_registersAUX_ARB_CONTROLAUX_SW_DATAAUX_SW_CONTROLAUX_INTERRUPT_CONTROLAUX_SW_STATUSAUXN_IMPCALAUXP_IMPCALAUX_RESET_MASKAUX_TIMEOUT_PERIODSW_AUX_TIMEOUT_PERIOD_MULTIPLIERdce_aux_funcsdce110_aux_registers_maskAUX_ENAUX_RESETAUX_RESET_DONEAUX_REG_RW_CNTL_STATUSAUX_SW_USE_AUX_REG_REQAUX_SW_DONE_USING_AUX_REGAUX_SW_AUTOINCREMENT_DISABLEAUX_SW_DATA_RWAUX_SW_INDEXAUX_SW_GOAUX_SW_REPLY_BYTE_COUNTAUX_SW_DONEAUX_SW_DONE_ACKAUXN_IMPCAL_ENABLEAUXP_IMPCAL_ENABLEAUXN_IMPCAL_OVERRIDE_ENABLEAUXP_IMPCAL_OVERRIDE_ENABLEAUX_RX_TIMEOUT_LENAUX_RX_TIMEOUT_LEN_MULAUXN_CALOUT_ERROR_AKAUXP_CALOUT_ERROR_AKAUX_SW_START_DELAYAUX_SW_WR_BYTESdce110_aux_registers_shiftaux_arb_controlaux_sw_dataaux_sw_controlaux_interrupt_controlaux_dphy_rx_control1aux_dphy_rx_control0aux_sw_statusaux_engine_dce110polling_timeout_perioddce_abm_shiftABM1_HG_NUM_OF_BINS_SELABM1_HG_VMAX_SELABM1_HG_BIN_BITWIDTH_SIZE_SELABM1_IPCSC_COEFF_SEL_RABM1_IPCSC_COEFF_SEL_GABM1_IPCSC_COEFF_SEL_BBL1_PWM_CURRENT_ABM_LEVELBL1_PWM_TARGET_ABM_LEVELBL1_PWM_USER_LEVELABM1_LS_MIN_PIXEL_VALUE_THRESABM1_LS_MAX_PIXEL_VALUE_THRESABM1_HG_REG_READ_MISSED_FRAME_CLEARABM1_LS_REG_READ_MISSED_FRAME_CLEARABM1_BL_REG_READ_MISSED_FRAME_CLEARMASTER_COMM_CMD_REG_BYTE1MASTER_COMM_CMD_REG_BYTE2ABM1_HG_BIN_33_40_SHIFT_INDEXABM1_HG_BIN_33_64_SHIFT_FLAGABM1_HG_BIN_41_48_SHIFT_INDEXABM1_HG_BIN_49_56_SHIFT_INDEXABM1_HG_BIN_57_64_SHIFT_INDEXABM1_HG_RESULT_DATAABM1_HG_RESULT_INDEXABM1_ACE_SLOPE_DATAABM1_ACE_OFFSET_DATAABM1_ACE_OFFSET_SLOPE_INDEXABM1_ACE_THRES_INDEXABM1_ACE_IGNORE_MASTER_LOCK_ENABM1_ACE_READBACK_DB_REG_VALUE_ENABM1_ACE_DBUF_REG_UPDATE_PENDINGABM1_ACE_LOCKABM1_ACE_THRES_DATA_1ABM1_ACE_THRES_DATA_2dce_abm_maskdce_abm_registersDC_ABM1_HG_SAMPLE_RATEDC_ABM1_LS_SAMPLE_RATEBL1_PWM_BL_UPDATE_SAMPLE_RATEDC_ABM1_HG_MISC_CTRLDC_ABM1_IPCSC_COEFF_SELDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRESDC_ABM1_HGLS_REG_READ_PROGRESSDC_ABM1_ACE_OFFSET_SLOPE_0DC_ABM1_ACE_OFFSET_SLOPE_DATADC_ABM1_ACE_PWL_CNTLDC_ABM1_HG_BIN_33_40_SHIFT_INDEXDC_ABM1_HG_BIN_33_64_SHIFT_FLAGDC_ABM1_HG_BIN_41_48_SHIFT_INDEXDC_ABM1_HG_BIN_49_56_SHIFT_INDEXDC_ABM1_HG_BIN_57_64_SHIFT_INDEXDC_ABM1_HG_RESULT_DATADC_ABM1_HG_RESULT_INDEXDC_ABM1_ACE_THRES_DATADC_ABM1_ACE_THRES_12OBJECT_TYPE_UNKNOWNOBJECT_TYPE_GPUOBJECT_TYPE_ENCODEROBJECT_TYPE_CONNECTOROBJECT_TYPE_ROUTEROBJECT_TYPE_GENERICOBJECT_TYPE_AUDIOOBJECT_TYPE_CONTROLLEROBJECT_TYPE_CLOCK_SOURCEOBJECT_TYPE_ENGINEOBJECT_TYPE_COUNTdm_lb_10dm_lb_8dm_lb_6dm_lb_12dm_lb_16dm_lb_19hubp_vmid_usagemmhubbub_wbif_modePACKED_444PACKED_444_FP16PLANAR_420_8BPCPLANAR_420_10BPCdc_bounding_box_max_clkmax_dcfclk_mhzmax_dispclk_mhzmax_dppclk_mhzmax_phyclk_mhzNV_NAVI10_P_A0NV_NAVI12_P_A0NV_NAVI14_M_A0NV_SIENNA_CICHLID_P_A0NV_DIMGREY_CAVEFISH_P_A0NV_BEIGE_GOBY_P_A0NV_UNKNOWNdcn30_resource_pooldcn_hubbub_registersDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_ADCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_ADCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_ADCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_ADCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_ADCHUBBUB_ARB_DATA_URGENCY_WATERMARK_BDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_BDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_BDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_BDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_BDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_CDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_CDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_CDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_CDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_CDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_DDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_DDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_DDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_DDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_DDCHUBBUB_ARB_WATERMARK_CHANGE_CNTLDCHUBBUB_ARB_SAT_LEVELDCHUBBUB_ARB_DF_REQ_OUTSTANDDCHUBBUB_ARB_DRAM_STATE_CNTLDCHUBBUB_TEST_DEBUG_INDEXDCHUBBUB_TEST_DEBUG_DATADCHUBBUB_SDPIF_FB_TOPDCHUBBUB_SOFT_RESETDCN_VM_FB_LOCATION_BASEDCN_VM_FB_LOCATION_TOPDCN_VM_FB_OFFSETDCN_VM_AGP_BOTDCN_VM_AGP_TOPDCN_VM_AGP_BASEDCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSBDCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSBDCN_VM_FAULT_ADDR_MSBDCN_VM_FAULT_ADDR_LSBDCN_VM_FAULT_CNTLDCN_VM_FAULT_STATUSDCHUBBUB_ARB_FRAC_URG_BW_NOM_ADCHUBBUB_ARB_FRAC_URG_BW_NOM_BDCHUBBUB_ARB_FRAC_URG_BW_NOM_CDCHUBBUB_ARB_FRAC_URG_BW_NOM_DDCHUBBUB_ARB_FRAC_URG_BW_FLIP_ADCHUBBUB_ARB_FRAC_URG_BW_FLIP_BDCHUBBUB_ARB_FRAC_URG_BW_FLIP_CDCHUBBUB_ARB_FRAC_URG_BW_FLIP_DDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_ADCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_BDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_CDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_DDCHVM_CTRL0DCHVM_MEM_CTRLDCHVM_CLK_CTRLDCHVM_RIOMMU_CTRL0DCHVM_RIOMMU_STAT0DCHUBBUB_DET0_CTRLDCHUBBUB_DET1_CTRLDCHUBBUB_DET2_CTRLDCHUBBUB_DET3_CTRLDCHUBBUB_COMPBUF_CTRLCOMPBUF_RESERVED_SPACEDCHUBBUB_DEBUG_CTRL_0DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_ADCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_ADCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_BDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_BDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_CDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_CDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_DDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_DDCHUBBUB_ARB_USR_RETRAINING_CNTLDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_ADCHUBBUB_ARB_USR_RETRAINING_WATERMARK_BDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_CDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_DDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_ADCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_BDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_CDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_DDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_ADCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_BDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_CDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_DDCHUBBUB_ARB_MALL_CNTLSDPIF_REQUEST_RATE_LIMITDCHUBBUB_SDPIF_CFG0DCHUBBUB_SDPIF_CFG1DCHUBBUB_CLOCK_CNTLDCHUBBUB_MEM_PWR_MODE_CTRLDCHUBBUB_ARB_QOS_FORCEdcn_hubbub_shiftDCHUBBUB_ARB_WATERMARK_CHANGE_REQUESTDCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLEDCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUEDCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLEDCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUEDCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLEDCHUBBUB_ARB_MIN_REQ_OUTSTANDDCHUBBUB_GLOBAL_SOFT_RESETSDPIF_FB_TOPDCN_VM_ERROR_STATUS_CLEARDCN_VM_ERROR_STATUS_MODEDCN_VM_ERROR_INTERRUPT_ENABLEDCN_VM_RANGE_FAULT_DISABLEDCN_VM_PRQ_FAULT_DISABLEDCN_VM_ERROR_STATUSDCN_VM_ERROR_VMIDDCN_VM_ERROR_TABLE_LEVELDCN_VM_ERROR_PIPEDCN_VM_ERROR_INTERRUPT_STATUSDCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLDDCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_ADCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_BDCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_CDCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_DDCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_ADCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_BDCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_CDCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_DDCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_ADCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_BDCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_CDCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_DDCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_ADCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_BDCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_CDCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_DDCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLDHOSTVM_INIT_REQHVM_GPUVMRET_PWR_REQ_DISHVM_GPUVMRET_FORCE_REQHVM_GPUVMRET_POWER_STATUSHVM_DISPCLK_R_GATE_DISHVM_DISPCLK_G_GATE_DISHVM_DCFCLK_R_GATE_DISHVM_DCFCLK_G_GATE_DISTR_REQ_REQCLKREQ_MODETW_RSP_COMPCLKREQ_MODEHOSTVM_PREFETCH_REQHOSTVM_POWERSTATUSRIOMMU_ACTIVEHOSTVM_PREFETCH_DONEDET_DEPTHDET0_SIZEDET1_SIZEDET2_SIZEDET3_SIZEDET0_SIZE_CURRENTDET1_SIZE_CURRENTDET2_SIZE_CURRENTDET3_SIZE_CURRENTCOMPBUF_SIZECOMPBUF_SIZE_CURRENTCONFIG_ERRORDISPCLK_R_DCHUBBUB_GATE_DISDCFCLK_R_DCHUBBUB_GATE_DISSDPIF_MAX_NUM_OUTSTANDINGDCHUBBUB_ARB_MAX_REQ_OUTSTANDSDPIF_PORT_CONTROLDET_MEM_PWR_LS_MODEDCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUEDCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLEDCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PSTATE_CHANGE_REQUESTDCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PRE_CSTATEMALL_PREFETCH_COMPLETEMALL_IN_USEDCHUBBUB_FGCG_REP_DISDCHUBBUB_ARB_ALLOW_CSTATE_DEEPSLEEP_LEGACY_MODEdcn_hubbub_maskdcn_vmid_registersCNTLPAGE_TABLE_BASE_ADDR_HI32PAGE_TABLE_BASE_ADDR_LO32PAGE_TABLE_START_ADDR_HI32PAGE_TABLE_START_ADDR_LO32PAGE_TABLE_END_ADDR_HI32PAGE_TABLE_END_ADDR_LO32dcn20_vmid_shiftVM_CONTEXT0_PAGE_TABLE_DEPTHVM_CONTEXT0_PAGE_TABLE_BLOCK_SIZEVM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32dcn20_vmid_maskdcn20_vmiddcn20_hubbubdebug_test_index_pstatedetile_buf_sizecrb_size_segscompbuf_size_segmentspixel_chunk_sizedet0_sizedet1_sizedet2_sizedet3_sizedcn20_mpc_registersMPCC_TOP_SELMPCC_BOT_SELMPCC_CONTROLMPCC_STATUSMPCC_OPP_IDMPCC_BG_G_YMPCC_BG_R_CRMPCC_BG_B_CBMPCC_SM_CONTROLMUXMPCC_UPDATE_LOCK_SELCURMPCC_TOP_GAINMPCC_BOT_GAIN_INSIDEMPCC_BOT_GAIN_OUTSIDEMPCC_OGAM_RAMA_START_CNTL_BMPCC_OGAM_RAMA_START_CNTL_GMPCC_OGAM_RAMA_START_CNTL_RMPCC_OGAM_RAMA_SLOPE_CNTL_BMPCC_OGAM_RAMA_SLOPE_CNTL_GMPCC_OGAM_RAMA_SLOPE_CNTL_RMPCC_OGAM_RAMA_END_CNTL1_BMPCC_OGAM_RAMA_END_CNTL2_BMPCC_OGAM_RAMA_END_CNTL1_GMPCC_OGAM_RAMA_END_CNTL2_GMPCC_OGAM_RAMA_END_CNTL1_RMPCC_OGAM_RAMA_END_CNTL2_RMPCC_OGAM_RAMA_REGION_0_1MPCC_OGAM_RAMA_REGION_32_33MPCC_OGAM_RAMB_START_CNTL_BMPCC_OGAM_RAMB_START_CNTL_GMPCC_OGAM_RAMB_START_CNTL_RMPCC_OGAM_RAMB_SLOPE_CNTL_BMPCC_OGAM_RAMB_SLOPE_CNTL_GMPCC_OGAM_RAMB_SLOPE_CNTL_RMPCC_OGAM_RAMB_END_CNTL1_BMPCC_OGAM_RAMB_END_CNTL2_BMPCC_OGAM_RAMB_END_CNTL1_GMPCC_OGAM_RAMB_END_CNTL2_GMPCC_OGAM_RAMB_END_CNTL1_RMPCC_OGAM_RAMB_END_CNTL2_RMPCC_OGAM_RAMB_REGION_0_1MPCC_OGAM_RAMB_REGION_32_33MPCC_MEM_PWR_CTRLMPCC_OGAM_LUT_INDEXMPCC_OGAM_LUT_RAM_CONTROLMPCC_OGAM_LUT_DATAMPCC_OGAM_MODEMPC_OCSC_TEST_DEBUG_DATAMPC_OCSC_TEST_DEBUG_INDEXCSC_MODECSC_C11_C12_ACSC_C33_C34_ACSC_C11_C12_BCSC_C33_C34_BDENORM_CLAMP_G_YDENORM_CLAMP_B_CBdcn20_mpc_shiftMPCC_MODEMPCC_ALPHA_BLND_MODEMPCC_ALPHA_MULTIPLIED_MODEMPCC_BLND_ACTIVE_OVERLAP_ONLYMPCC_GLOBAL_ALPHAMPCC_GLOBAL_GAINMPCC_IDLEMPCC_BUSYMPCC_SM_ENMPCC_SM_MODEMPCC_SM_FRAME_ALTMPCC_SM_FIELD_ALTMPCC_SM_FORCE_NEXT_FRAME_POLMPCC_SM_FORCE_NEXT_TOP_POLMPC_OUT_MUXCUR_VUPDATE_LOCK_SETMPCC_BG_BPCMPCC_BOT_GAIN_MODEMPC_OCSC_TEST_DEBUG_DATA_OCSC_MODEMPC_OCSC_MODEMPC_OCSC_C11_AMPC_OCSC_C12_AMPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSETMPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTSMPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSETMPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTSMPCC_OGAM_RAMA_EXP_REGION_END_BMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_BMPCC_OGAM_RAMA_EXP_REGION_END_BASE_BMPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_BMPCC_OGAM_RAMA_EXP_REGION_START_BMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_BMPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSETMPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTSMPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSETMPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTSMPCC_OGAM_RAMB_EXP_REGION_END_BMPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_BMPCC_OGAM_RAMB_EXP_REGION_END_BASE_BMPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_BMPCC_OGAM_RAMB_EXP_REGION_START_BMPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_BMPCC_OGAM_MEM_PWR_FORCEMPCC_OGAM_LUT_WRITE_EN_MASKMPCC_OGAM_LUT_RAM_SELMPCC_OGAM_CONFIG_STATUSMPC_OUT_DENORM_MODEMPC_OUT_DENORM_CLAMP_MAX_R_CRMPC_OUT_DENORM_CLAMP_MIN_R_CRMPC_OUT_DENORM_CLAMP_MAX_G_YMPC_OUT_DENORM_CLAMP_MIN_G_YMPC_OUT_DENORM_CLAMP_MAX_B_CBMPC_OUT_DENORM_CLAMP_MIN_B_CBMPCC_DISABLEDMPCC_OGAM_MEM_PWR_DISdcn20_mpc_maskdcn20_mpcmpcc_in_use_masknum_mpccmpc_regsmpc_shiftmpc_maskdcn30_mpc_registersDWB_MUXMPCC_GAMUT_REMAP_COEF_FORMATMPCC_GAMUT_REMAP_MODEMPC_GAMUT_REMAP_C11_C12_AMPC_GAMUT_REMAP_C33_C34_AMPC_GAMUT_REMAP_C11_C12_BMPC_GAMUT_REMAP_C33_C34_BMPC_RMU_CONTROLMPC_RMU_MEM_PWR_CTRLSHAPER_CONTROLSHAPER_OFFSET_RSHAPER_OFFSET_GSHAPER_OFFSET_BSHAPER_SCALE_RSHAPER_SCALE_G_BSHAPER_LUT_INDEXSHAPER_LUT_DATASHAPER_LUT_WRITE_EN_MASKSHAPER_RAMA_START_CNTL_BSHAPER_RAMA_START_CNTL_GSHAPER_RAMA_START_CNTL_RSHAPER_RAMA_END_CNTL_BSHAPER_RAMA_END_CNTL_GSHAPER_RAMA_END_CNTL_RSHAPER_RAMA_REGION_0_1SHAPER_RAMA_REGION_2_3SHAPER_RAMA_REGION_4_5SHAPER_RAMA_REGION_6_7SHAPER_RAMA_REGION_8_9SHAPER_RAMA_REGION_10_11SHAPER_RAMA_REGION_12_13SHAPER_RAMA_REGION_14_15SHAPER_RAMA_REGION_16_17SHAPER_RAMA_REGION_18_19SHAPER_RAMA_REGION_20_21SHAPER_RAMA_REGION_22_23SHAPER_RAMA_REGION_24_25SHAPER_RAMA_REGION_26_27SHAPER_RAMA_REGION_28_29SHAPER_RAMA_REGION_30_31SHAPER_RAMA_REGION_32_33MPCC_OGAM_RAMA_START_SLOPE_CNTL_BMPCC_OGAM_RAMA_START_SLOPE_CNTL_GMPCC_OGAM_RAMA_START_SLOPE_CNTL_RMPCC_OGAM_RAMA_OFFSET_BMPCC_OGAM_RAMA_OFFSET_GMPCC_OGAM_RAMA_OFFSET_RMPCC_OGAM_RAMA_START_BASE_CNTL_BMPCC_OGAM_RAMA_START_BASE_CNTL_GMPCC_OGAM_RAMA_START_BASE_CNTL_RSHAPER_RAMB_START_CNTL_BSHAPER_RAMB_START_CNTL_GSHAPER_RAMB_START_CNTL_RSHAPER_RAMB_END_CNTL_BSHAPER_RAMB_END_CNTL_GSHAPER_RAMB_END_CNTL_RSHAPER_RAMB_REGION_0_1SHAPER_RAMB_REGION_2_3SHAPER_RAMB_REGION_4_5SHAPER_RAMB_REGION_6_7SHAPER_RAMB_REGION_8_9SHAPER_RAMB_REGION_10_11SHAPER_RAMB_REGION_12_13SHAPER_RAMB_REGION_14_15SHAPER_RAMB_REGION_16_17SHAPER_RAMB_REGION_18_19SHAPER_RAMB_REGION_20_21SHAPER_RAMB_REGION_22_23SHAPER_RAMB_REGION_24_25SHAPER_RAMB_REGION_26_27SHAPER_RAMB_REGION_28_29SHAPER_RAMB_REGION_30_31SHAPER_RAMB_REGION_32_33RMU_3DLUT_MODERMU_3DLUT_INDEXRMU_3DLUT_DATARMU_3DLUT_DATA_30BITRMU_3DLUT_READ_WRITE_CONTROLRMU_3DLUT_OUT_NORM_FACTORRMU_3DLUT_OUT_OFFSET_RRMU_3DLUT_OUT_OFFSET_GRMU_3DLUT_OUT_OFFSET_BMPCC_OGAM_RAMB_START_SLOPE_CNTL_BMPCC_OGAM_RAMB_START_SLOPE_CNTL_GMPCC_OGAM_RAMB_START_SLOPE_CNTL_RMPCC_OGAM_CONTROLMPCC_OGAM_LUT_CONTROLMPCC_OGAM_RAMB_OFFSET_BMPCC_OGAM_RAMB_OFFSET_GMPCC_OGAM_RAMB_OFFSET_RMPCC_OGAM_RAMB_START_BASE_CNTL_BMPCC_OGAM_RAMB_START_BASE_CNTL_GMPCC_OGAM_RAMB_START_BASE_CNTL_RMPC_OUT_CSC_COEF_FORMATMPCC_MOVABLE_CM_LOCATION_CONTROLMPCC_MCM_SHAPER_CONTROLMPCC_MCM_SHAPER_OFFSET_RMPCC_MCM_SHAPER_OFFSET_GMPCC_MCM_SHAPER_OFFSET_BMPCC_MCM_SHAPER_SCALE_RMPCC_MCM_SHAPER_SCALE_G_BMPCC_MCM_SHAPER_LUT_INDEXMPCC_MCM_SHAPER_LUT_DATAMPCC_MCM_SHAPER_LUT_WRITE_EN_MASKMPCC_MCM_SHAPER_RAMA_START_CNTL_BMPCC_MCM_SHAPER_RAMA_START_CNTL_GMPCC_MCM_SHAPER_RAMA_START_CNTL_RMPCC_MCM_SHAPER_RAMA_END_CNTL_BMPCC_MCM_SHAPER_RAMA_END_CNTL_GMPCC_MCM_SHAPER_RAMA_END_CNTL_RMPCC_MCM_SHAPER_RAMA_REGION_0_1MPCC_MCM_SHAPER_RAMA_REGION_2_3MPCC_MCM_SHAPER_RAMA_REGION_4_5MPCC_MCM_SHAPER_RAMA_REGION_6_7MPCC_MCM_SHAPER_RAMA_REGION_8_9MPCC_MCM_SHAPER_RAMA_REGION_10_11MPCC_MCM_SHAPER_RAMA_REGION_12_13MPCC_MCM_SHAPER_RAMA_REGION_14_15MPCC_MCM_SHAPER_RAMA_REGION_16_17MPCC_MCM_SHAPER_RAMA_REGION_18_19MPCC_MCM_SHAPER_RAMA_REGION_20_21MPCC_MCM_SHAPER_RAMA_REGION_22_23MPCC_MCM_SHAPER_RAMA_REGION_24_25MPCC_MCM_SHAPER_RAMA_REGION_26_27MPCC_MCM_SHAPER_RAMA_REGION_28_29MPCC_MCM_SHAPER_RAMA_REGION_30_31MPCC_MCM_SHAPER_RAMA_REGION_32_33MPCC_MCM_SHAPER_RAMB_START_CNTL_BMPCC_MCM_SHAPER_RAMB_START_CNTL_GMPCC_MCM_SHAPER_RAMB_START_CNTL_RMPCC_MCM_SHAPER_RAMB_END_CNTL_BMPCC_MCM_SHAPER_RAMB_END_CNTL_GMPCC_MCM_SHAPER_RAMB_END_CNTL_RMPCC_MCM_SHAPER_RAMB_REGION_0_1MPCC_MCM_SHAPER_RAMB_REGION_2_3MPCC_MCM_SHAPER_RAMB_REGION_4_5MPCC_MCM_SHAPER_RAMB_REGION_6_7MPCC_MCM_SHAPER_RAMB_REGION_8_9MPCC_MCM_SHAPER_RAMB_REGION_10_11MPCC_MCM_SHAPER_RAMB_REGION_12_13MPCC_MCM_SHAPER_RAMB_REGION_14_15MPCC_MCM_SHAPER_RAMB_REGION_16_17MPCC_MCM_SHAPER_RAMB_REGION_18_19MPCC_MCM_SHAPER_RAMB_REGION_20_21MPCC_MCM_SHAPER_RAMB_REGION_22_23MPCC_MCM_SHAPER_RAMB_REGION_24_25MPCC_MCM_SHAPER_RAMB_REGION_26_27MPCC_MCM_SHAPER_RAMB_REGION_28_29MPCC_MCM_SHAPER_RAMB_REGION_30_31MPCC_MCM_SHAPER_RAMB_REGION_32_33MPCC_MCM_3DLUT_MODEMPCC_MCM_3DLUT_INDEXMPCC_MCM_3DLUT_DATAMPCC_MCM_3DLUT_DATA_30BITMPCC_MCM_3DLUT_READ_WRITE_CONTROLMPCC_MCM_3DLUT_OUT_NORM_FACTORMPCC_MCM_3DLUT_OUT_OFFSET_RMPCC_MCM_3DLUT_OUT_OFFSET_GMPCC_MCM_3DLUT_OUT_OFFSET_BMPCC_MCM_1DLUT_CONTROLMPCC_MCM_1DLUT_LUT_INDEXMPCC_MCM_1DLUT_LUT_DATAMPCC_MCM_1DLUT_LUT_CONTROLMPCC_MCM_1DLUT_RAMA_START_CNTL_BMPCC_MCM_1DLUT_RAMA_START_CNTL_GMPCC_MCM_1DLUT_RAMA_START_CNTL_RMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_BMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_GMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_RMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_BMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_GMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_RMPCC_MCM_1DLUT_RAMA_END_CNTL1_BMPCC_MCM_1DLUT_RAMA_END_CNTL2_BMPCC_MCM_1DLUT_RAMA_END_CNTL1_GMPCC_MCM_1DLUT_RAMA_END_CNTL2_GMPCC_MCM_1DLUT_RAMA_END_CNTL1_RMPCC_MCM_1DLUT_RAMA_END_CNTL2_RMPCC_MCM_1DLUT_RAMA_OFFSET_BMPCC_MCM_1DLUT_RAMA_OFFSET_GMPCC_MCM_1DLUT_RAMA_OFFSET_RMPCC_MCM_1DLUT_RAMA_REGION_0_1MPCC_MCM_1DLUT_RAMA_REGION_2_3MPCC_MCM_1DLUT_RAMA_REGION_4_5MPCC_MCM_1DLUT_RAMA_REGION_6_7MPCC_MCM_1DLUT_RAMA_REGION_8_9MPCC_MCM_1DLUT_RAMA_REGION_10_11MPCC_MCM_1DLUT_RAMA_REGION_12_13MPCC_MCM_1DLUT_RAMA_REGION_14_15MPCC_MCM_1DLUT_RAMA_REGION_16_17MPCC_MCM_1DLUT_RAMA_REGION_18_19MPCC_MCM_1DLUT_RAMA_REGION_20_21MPCC_MCM_1DLUT_RAMA_REGION_22_23MPCC_MCM_1DLUT_RAMA_REGION_24_25MPCC_MCM_1DLUT_RAMA_REGION_26_27MPCC_MCM_1DLUT_RAMA_REGION_28_29MPCC_MCM_1DLUT_RAMA_REGION_30_31MPCC_MCM_1DLUT_RAMA_REGION_32_33MPCC_MCM_1DLUT_RAMB_START_CNTL_BMPCC_MCM_1DLUT_RAMB_START_CNTL_GMPCC_MCM_1DLUT_RAMB_START_CNTL_RMPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_BMPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_GMPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_RMPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_BMPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_GMPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_RMPCC_MCM_1DLUT_RAMB_END_CNTL1_BMPCC_MCM_1DLUT_RAMB_END_CNTL2_BMPCC_MCM_1DLUT_RAMB_END_CNTL1_GMPCC_MCM_1DLUT_RAMB_END_CNTL2_GMPCC_MCM_1DLUT_RAMB_END_CNTL1_RMPCC_MCM_1DLUT_RAMB_END_CNTL2_RMPCC_MCM_1DLUT_RAMB_OFFSET_BMPCC_MCM_1DLUT_RAMB_OFFSET_GMPCC_MCM_1DLUT_RAMB_OFFSET_RMPCC_MCM_1DLUT_RAMB_REGION_0_1MPCC_MCM_1DLUT_RAMB_REGION_2_3MPCC_MCM_1DLUT_RAMB_REGION_4_5MPCC_MCM_1DLUT_RAMB_REGION_6_7MPCC_MCM_1DLUT_RAMB_REGION_8_9MPCC_MCM_1DLUT_RAMB_REGION_10_11MPCC_MCM_1DLUT_RAMB_REGION_12_13MPCC_MCM_1DLUT_RAMB_REGION_14_15MPCC_MCM_1DLUT_RAMB_REGION_16_17MPCC_MCM_1DLUT_RAMB_REGION_18_19MPCC_MCM_1DLUT_RAMB_REGION_20_21MPCC_MCM_1DLUT_RAMB_REGION_22_23MPCC_MCM_1DLUT_RAMB_REGION_24_25MPCC_MCM_1DLUT_RAMB_REGION_26_27MPCC_MCM_1DLUT_RAMB_REGION_28_29MPCC_MCM_1DLUT_RAMB_REGION_30_31MPCC_MCM_1DLUT_RAMB_REGION_32_33MPCC_MCM_MEM_PWR_CTRLdcn30_mpc_shiftMPC_DWB0_MUXMPC_DWB0_MUX_STATUSMPC_OUT_RATE_CONTROLMPC_OUT_RATE_CONTROL_DISABLEMPC_OUT_FLOW_CONTROL_MODEMPC_OUT_FLOW_CONTROL_COUNTMPCC_GAMUT_REMAP_MODE_CURRENTMPCC_GAMUT_REMAP_C11_AMPCC_GAMUT_REMAP_C12_AMPC_RMU0_MUXMPC_RMU1_MUXMPC_RMU0_MUX_STATUSMPC_RMU1_MUX_STATUSMPC_RMU0_MEM_PWR_FORCEMPC_RMU0_MEM_PWR_DISMPC_RMU0_MEM_LOW_PWR_MODEMPC_RMU0_SHAPER_MEM_PWR_STATEMPC_RMU0_3DLUT_MEM_PWR_STATEMPC_RMU1_MEM_PWR_FORCEMPC_RMU1_MEM_PWR_DISMPC_RMU1_MEM_LOW_PWR_MODEMPC_RMU1_SHAPER_MEM_PWR_STATEMPC_RMU1_3DLUT_MEM_PWR_STATEMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_BMPCC_OGAM_RAMA_EXP_REGION_START_BASE_BMPCC_OGAM_SELECTMPCC_OGAM_PWL_DISABLEMPCC_OGAM_MODE_CURRENTMPCC_OGAM_SELECT_CURRENTMPCC_OGAM_LUT_WRITE_COLOR_MASKMPCC_OGAM_LUT_READ_COLOR_SELMPCC_OGAM_LUT_READ_DBGMPCC_OGAM_LUT_HOST_SELMPCC_OGAM_LUT_CONFIG_MODEMPCC_OGAM_LUT_STATUSMPCC_OGAM_MEM_LOW_PWR_MODEMPCC_OGAM_MEM_PWR_STATEMPC_RMU_3DLUT_MODEMPC_RMU_3DLUT_SIZEMPC_RMU_3DLUT_MODE_CURRENTMPC_RMU_3DLUT_WRITE_EN_MASKMPC_RMU_3DLUT_RAM_SELMPC_RMU_3DLUT_30BIT_ENMPC_RMU_3DLUT_CONFIG_STATUSMPC_RMU_3DLUT_READ_SELMPC_RMU_3DLUT_INDEXMPC_RMU_3DLUT_DATA0MPC_RMU_3DLUT_DATA1MPC_RMU_3DLUT_DATA_30BITMPC_RMU_SHAPER_LUT_MODEMPC_RMU_SHAPER_LUT_MODE_CURRENTMPC_RMU_SHAPER_OFFSET_RMPC_RMU_SHAPER_OFFSET_GMPC_RMU_SHAPER_OFFSET_BMPC_RMU_SHAPER_SCALE_RMPC_RMU_SHAPER_SCALE_GMPC_RMU_SHAPER_SCALE_BMPC_RMU_SHAPER_LUT_INDEXMPC_RMU_SHAPER_LUT_DATAMPC_RMU_SHAPER_LUT_WRITE_EN_MASKMPC_RMU_SHAPER_LUT_WRITE_SELMPC_RMU_SHAPER_CONFIG_STATUSMPC_RMU_SHAPER_RAMA_EXP_REGION_START_BMPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_BMPC_RMU_SHAPER_RAMA_EXP_REGION_END_BMPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_BMPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSETMPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTSMPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSETMPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTSMPC_RMU_SHAPER_MODE_CURRENTMPCC_MOVABLE_CM_LOCATION_CNTLMPCC_MOVABLE_CM_LOCATION_CNTL_CURRENTMPCC_MCM_SHAPER_MEM_PWR_FORCEMPCC_MCM_SHAPER_MEM_PWR_DISMPCC_MCM_SHAPER_MEM_LOW_PWR_MODEMPCC_MCM_3DLUT_MEM_PWR_FORCEMPCC_MCM_3DLUT_MEM_PWR_DISMPCC_MCM_3DLUT_MEM_LOW_PWR_MODEMPCC_MCM_1DLUT_MEM_PWR_FORCEMPCC_MCM_1DLUT_MEM_PWR_DISMPCC_MCM_1DLUT_MEM_LOW_PWR_MODEMPCC_MCM_SHAPER_MEM_PWR_STATEMPCC_MCM_3DLUT_MEM_PWR_STATEMPCC_MCM_1DLUT_MEM_PWR_STATEMPCC_MCM_3DLUT_SIZEMPCC_MCM_3DLUT_MODE_CURRENTMPCC_MCM_3DLUT_WRITE_EN_MASKMPCC_MCM_3DLUT_RAM_SELMPCC_MCM_3DLUT_30BIT_ENMPCC_MCM_3DLUT_CONFIG_STATUSMPCC_MCM_3DLUT_READ_SELMPCC_MCM_3DLUT_DATA0MPCC_MCM_3DLUT_DATA1MPCC_MCM_SHAPER_LUT_MODEMPCC_MCM_SHAPER_MODE_CURRENTMPCC_MCM_SHAPER_SCALE_GMPCC_MCM_SHAPER_SCALE_BMPCC_MCM_SHAPER_LUT_WRITE_SELMPCC_MCM_SHAPER_CONFIG_STATUSMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_BMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_BMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_BMPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSETMPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTSMPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSETMPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTSMPCC_MCM_1DLUT_MODEMPCC_MCM_1DLUT_SELECTMPCC_MCM_1DLUT_PWL_DISABLEMPCC_MCM_1DLUT_MODE_CURRENTMPCC_MCM_1DLUT_SELECT_CURRENTMPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASKMPCC_MCM_1DLUT_LUT_READ_COLOR_SELMPCC_MCM_1DLUT_LUT_HOST_SELMPCC_MCM_1DLUT_LUT_CONFIG_MODEMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_BMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_BMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_BMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_BMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_BMPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSETMPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTSMPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSETMPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTSdcn30_mpc_maskdcn30_mpcnum_rmudcn_hubp_statedlg_attrttu_attrinuse_addr_hiinuse_addr_loh_mirror_endcc_enblank_enclock_enunderflow_statusttu_disableprimary_surface_addr_loprimary_surface_addr_hiprimary_meta_addr_loprimary_meta_addr_hiuclk_pstate_forcehubp_cntldcn_hubp2_registersDCHUBP_CNTLHUBPREQ_DEBUG_DBHUBPREQ_DEBUGDCSURF_ADDR_CONFIGDCSURF_TILING_CONFIGDCSURF_SURFACE_PITCHDCSURF_SURFACE_PITCH_CDCSURF_SURFACE_CONFIGDCSURF_FLIP_CONTROLDCSURF_PRI_VIEWPORT_DIMENSIONDCSURF_PRI_VIEWPORT_STARTDCSURF_SEC_VIEWPORT_DIMENSIONDCSURF_SEC_VIEWPORT_STARTDCSURF_PRI_VIEWPORT_DIMENSION_CDCSURF_PRI_VIEWPORT_START_CDCSURF_SEC_VIEWPORT_DIMENSION_CDCSURF_SEC_VIEWPORT_START_CDCSURF_SECONDARY_SURFACE_ADDRESS_HIGHDCSURF_SECONDARY_SURFACE_ADDRESSDCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGHDCSURF_PRIMARY_META_SURFACE_ADDRESSDCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGHDCSURF_SECONDARY_META_SURFACE_ADDRESSDCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_CDCSURF_SECONDARY_SURFACE_ADDRESS_CDCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_CDCSURF_PRIMARY_META_SURFACE_ADDRESS_CDCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_CDCSURF_SECONDARY_META_SURFACE_ADDRESS_CDCSURF_SURFACE_INUSEDCSURF_SURFACE_INUSE_HIGHDCSURF_SURFACE_INUSE_CDCSURF_SURFACE_INUSE_HIGH_CDCSURF_SURFACE_EARLIEST_INUSEDCSURF_SURFACE_EARLIEST_INUSE_HIGHDCSURF_SURFACE_EARLIEST_INUSE_CDCSURF_SURFACE_EARLIEST_INUSE_HIGH_CDCSURF_SURFACE_FLIP_INTERRUPTHUBPRET_CONTROLHUBPRET_READ_LINE_STATUSDCN_EXPANSION_MODEDCHUBP_REQ_SIZE_CONFIGDCHUBP_REQ_SIZE_CONFIG_CBLANK_OFFSET_0BLANK_OFFSET_1DST_DIMENSIONSDST_AFTER_SCALERPREFETCH_SETTINSPREFETCH_SETTINGSVBLANK_PARAMETERS_0REF_FREQ_TO_PIX_FREQVBLANK_PARAMETERS_1VBLANK_PARAMETERS_3NOM_PARAMETERS_0NOM_PARAMETERS_1NOM_PARAMETERS_4NOM_PARAMETERS_5PER_LINE_DELIVERY_PREPER_LINE_DELIVERYPREFETCH_SETTINS_CPREFETCH_SETTINGS_CVBLANK_PARAMETERS_2VBLANK_PARAMETERS_4N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GAM_RAMB_EXP_REGION_END_BASE_RCM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSETCM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTSCM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSETCM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTSCM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSETCM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTSCM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSETCM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTSCM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSETCM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTSCM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSETCM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTSCM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSETCM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTSCM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSETCM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTSCM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSETCM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTSCM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSETCM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTSCM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSETCM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTSCM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSETCM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTSCM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSETCM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTSCM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSETCM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTSCM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSETCM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTSCM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSETCM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTSCM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSETCM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTSCM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSETCM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTSCM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSETCM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTSCM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSETCM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTSCM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSETCM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTSCM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSETCM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTSCM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSETCM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTSCM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSETCM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTSCM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSETCM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTSCM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSETCM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTSCM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSETCM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTSCM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSETCM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTSCM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSETCM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTSCM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSETCM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTSCM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSETCM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTSCM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSETCM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTSCM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSETCM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTSCM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSETCM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTSCM_BLNDGAM_RAMA_EXP_REGION_START_BCM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_BCM_BLNDGAM_RAMA_EXP_REGION_START_GCM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_GCM_BLNDGAM_RAMA_EXP_REGION_START_RCM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_RCM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_BCM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_GCM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_RCM_BLNDGAM_RAMA_EXP_REGION_END_BCM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_BCM_BLNDGAM_RAMA_EXP_REGION_END_BASE_BCM_BLNDGAM_RAMA_EXP_REGION_END_GCM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_GCM_BLNDGAM_RAMA_EXP_REGION_END_BASE_GCM_BLNDGAM_RAMA_EXP_REGION_END_RCM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_RCM_BLNDGAM_RAMA_EXP_REGION_END_BASE_RCM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSETCM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTSCM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSETCM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTSCM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSETCM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTSCM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSETCM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTSCM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSETCM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTSCM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSETCM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTSCM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSETCM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTSCM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSETCM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTSCM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSETCM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTSCM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSETCM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTSCM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSETCM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTSCM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSETCM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTSCM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSETCM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTSCM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSETCM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTSCM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSETCM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTSCM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSETCM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTSCM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSETCM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTSCM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSETCM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTSCM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSETCM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTSCM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSETCM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTSCM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSETCM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTSCM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSETCM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTSCM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSETCM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTSCM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSETCM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTSCM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSETCM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTSCM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSETCM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTSCM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSETCM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTSCM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSETCM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTSCM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSETCM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTSCM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSETCM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTSCM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSETCM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTSCM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSETCM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTSCM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSETCM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTSCM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSETCM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTSCM_BLNDGAM_LUT_WRITE_EN_MASKCM_BLNDGAM_LUT_WRITE_SELCM_BLNDGAM_CONFIG_STATUSCM_BLNDGAM_LUT_INDEXBLNDGAM_MEM_PWR_FORCECM_3DLUT_MODECM_3DLUT_SIZECM_3DLUT_INDEXCM_3DLUT_DATA0CM_3DLUT_DATA1CM_3DLUT_DATA_30BITCM_3DLUT_WRITE_EN_MASKCM_3DLUT_RAM_SELCM_3DLUT_30BIT_ENCM_3DLUT_CONFIG_STATUSCM_3DLUT_READ_SELCM_SHAPER_LUT_MODECM_SHAPER_RAMB_EXP_REGION_START_BCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_BCM_SHAPER_RAMB_EXP_REGION_START_GCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_GCM_SHAPER_RAMB_EXP_REGION_START_RCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_RCM_SHAPER_RAMB_EXP_REGION_END_BCM_SHAPER_RAMB_EXP_REGION_END_BASE_BCM_SHAPER_RAMB_EXP_REGION_END_GCM_SHAPER_RAMB_EXP_REGION_END_BASE_GCM_SHAPER_RAMB_EXP_REGION_END_RCM_SHAPER_RAMB_EXP_REGION_END_BASE_RCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSETCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTSCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSETCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTSCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSETCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTSCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSETCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTSCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSETCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTSCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSETCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTSCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSETCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTSCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSETCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTSCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSETCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTSCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSETCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTSCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSETCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTSCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSETCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTSCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSETCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTSCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSETCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTSCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSETCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTSCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSETCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTSCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSETCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTSCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSETCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTSCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSETCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTSCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSETCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTSCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSETCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTSCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSETCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTSCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSETCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTSCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSETCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTSCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSETCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTSCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSETCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTSCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSETCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTSCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSETCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTSCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSETCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTSCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSETCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTSCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSETCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTSCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSETCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTSCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSETCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTSCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSETCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTSCM_SHAPER_RAMA_EXP_REGION_START_BCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_BCM_SHAPER_RAMA_EXP_REGION_START_GCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_GCM_SHAPER_RAMA_EXP_REGION_START_RCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_RCM_SHAPER_RAMA_EXP_REGION_END_BCM_SHAPER_RAMA_EXP_REGION_END_BASE_BCM_SHAPER_RAMA_EXP_REGION_END_GCM_SHAPER_RAMA_EXP_REGION_END_BASE_GCM_SHAPER_RAMA_EXP_REGION_END_RCM_SHAPER_RAMA_EXP_REGION_END_BASE_RCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSETCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTSCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSETCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTSCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSETCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTSCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSETCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTSCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSETCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTSCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSETCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTSCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSETCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTSCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSETCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTSCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSETCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTSCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSETCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTSCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSETCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTSCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSETCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTSCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSETCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTSCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSETCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTSCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSETCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTSCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSETCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTSCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSETCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTSCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSETCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTSCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSETCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTSCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSETCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTSCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSETCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTSCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSETCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTSCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSETCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTSCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSETCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTSCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSETCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTSCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSETCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTSCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSETCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTSCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSETCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTSCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSETCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTSCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSETCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTSCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSETCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTSCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSETCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTSCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSETCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTSCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSETCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTSCM_SHAPER_LUT_WRITE_EN_MASKCM_SHAPER_CONFIG_STATUSCM_SHAPER_LUT_WRITE_SELCM_SHAPER_LUT_INDEXCM_SHAPER_LUT_DATACM_DGAM_CONFIG_STATUSCM_ICSC_MODECM_ICSC_C11CM_ICSC_C12CM_ICSC_C33CM_ICSC_C34CM_BNS_BIAS_RCM_BNS_BIAS_GCM_BNS_BIAS_BCM_BNS_SCALE_RCM_BNS_SCALE_GCM_BNS_SCALE_BCM_DGAM_RAMB_EXP_REGION_START_BCM_DGAM_RAMB_EXP_REGION_START_SEGMENT_BCM_DGAM_RAMB_EXP_REGION_START_GCM_DGAM_RAMB_EXP_REGION_START_SEGMENT_GCM_DGAM_RAMB_EXP_REGION_START_RCM_DGAM_RAMB_EXP_REGION_START_SEGMENT_RCM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_BCM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_GCM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_RCM_DGAM_RAMB_EXP_REGION_END_BCM_DGAM_RAMB_EXP_REGION_END_SLOPE_BCM_DGAM_RAMB_EXP_REGION_END_BASE_BCM_DGAM_RAMB_EXP_REGION_END_GCM_DGAM_RAMB_EXP_REGION_END_SLOPE_GCM_DGAM_RAMB_EXP_REGION_END_BASE_GCM_DGAM_RAMB_EXP_REGION_END_RCM_DGAM_RAMB_EXP_REGION_END_SLOPE_RCM_DGAM_RAMB_EXP_REGION_END_BASE_RCM_DGAM_RAMB_EXP_REGION0_LUT_OFFSETCM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTSCM_DGAM_RAMB_EXP_REGION1_LUT_OFFSETCM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTSCM_DGAM_RAMB_EXP_REGION14_LUT_OFFSETCM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTSCM_DGAM_RAMB_EXP_REGION15_LUT_OFFSETCM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTSCM_DGAM_RAMA_EXP_REGION_START_BCM_DGAM_RAMA_EXP_REGION_START_SEGMENT_BCM_DGAM_RAMA_EXP_REGION_START_GCM_DGAM_RAMA_EXP_REGION_START_SEGMENT_GCM_DGAM_RAMA_EXP_REGION_START_RCM_DGAM_RAMA_EXP_REGION_START_SEGMENT_RCM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_BCM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_GCM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_RCM_DGAM_RAMA_EXP_REGION_END_BCM_DGAM_RAMA_EXP_REGION_END_SLOPE_BCM_DGAM_RAMA_EXP_REGION_END_BASE_BCM_DGAM_RAMA_EXP_REGION_END_GCM_DGAM_RAMA_EXP_REGION_END_SLOPE_GCM_DGAM_RAMA_EXP_REGION_END_BASE_GCM_DGAM_RAMA_EXP_REGION_END_RCM_DGAM_RAMA_EXP_REGION_END_SLOPE_RCM_DGAM_RAMA_EXP_REGION_END_BASE_RCM_DGAM_RAMA_EXP_REGION0_LUT_OFFSETCM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTSCM_DGAM_RAMA_EXP_REGION1_LUT_OFFSETCM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTSCM_DGAM_RAMA_EXP_REGION14_LUT_OFFSETCM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTSCM_DGAM_RAMA_EXP_REGION15_LUT_OFFSETCM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTSSHARED_MEM_PWR_DISCM_IGAM_LUT_FORMAT_RCM_IGAM_LUT_FORMAT_GCM_IGAM_LUT_FORMAT_BCM_IGAM_LUT_HOST_ENCM_IGAM_LUT_RW_MODECM_IGAM_LUT_WRITE_EN_MASKCM_IGAM_LUT_SELCM_IGAM_LUT_SEQ_COLORCM_IGAM_DGAM_CONFIG_STATUSCM_DGAM_LUT_WRITE_EN_MASKCM_DGAM_LUT_WRITE_SELCM_DGAM_LUT_INDEXCM_DGAM_LUT_DATACM_DGAM_LUT_MODECM_IGAM_LUT_MODECM_IGAM_INPUT_FORMATCM_IGAM_LUT_RW_INDEXCM_BYPASS_ENFORMAT_EXPANSION_M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RT_BASE_CNTL_BDWB_OGAM_RAMA_START_SLOPE_CNTL_BDWB_OGAM_RAMA_START_BASE_CNTL_GDWB_OGAM_RAMA_START_SLOPE_CNTL_GDWB_OGAM_RAMA_START_BASE_CNTL_RDWB_OGAM_RAMA_START_SLOPE_CNTL_RDWB_OGAM_RAMA_END_CNTL1_BDWB_OGAM_RAMA_END_CNTL2_BDWB_OGAM_RAMA_END_CNTL1_GDWB_OGAM_RAMA_END_CNTL2_GDWB_OGAM_RAMA_END_CNTL1_RDWB_OGAM_RAMA_END_CNTL2_RDWB_OGAM_RAMA_OFFSET_BDWB_OGAM_RAMA_OFFSET_GDWB_OGAM_RAMA_OFFSET_RDWB_OGAM_RAMA_REGION_0_1DWB_OGAM_RAMA_REGION_2_3DWB_OGAM_RAMA_REGION_4_5DWB_OGAM_RAMA_REGION_6_7DWB_OGAM_RAMA_REGION_8_9DWB_OGAM_RAMA_REGION_10_11DWB_OGAM_RAMA_REGION_12_13DWB_OGAM_RAMA_REGION_14_15DWB_OGAM_RAMA_REGION_16_17DWB_OGAM_RAMA_REGION_18_19DWB_OGAM_RAMA_REGION_20_21DWB_OGAM_RAMA_REGION_22_23DWB_OGAM_RAMA_REGION_24_25DWB_OGAM_RAMA_REGION_26_27DWB_OGAM_RAMA_REGION_28_29DWB_OGAM_RAMA_REGION_30_31DWB_OGAM_RAMA_REGION_32_33DWB_OGAM_RAMB_START_CNTL_BDWB_OGAM_RAMB_START_CNTL_GDWB_OGAM_RAMB_START_CNTL_RDWB_OGAM_RAMB_START_BASE_CNTL_BDWB_OGAM_RAMB_START_SLOPE_CNTL_BDWB_OGAM_RAMB_START_BASE_CNTL_GDWB_OGAM_RAMB_START_SLOPE_CNTL_GDWB_OGAM_RAMB_START_BASE_CNTL_RDWB_OGAM_RAMB_START_SLOPE_CNTL_RDWB_OGAM_RAMB_END_CNTL1_BDWB_OGAM_RAMB_END_CNTL2_BDWB_OGAM_RAMB_END_CNTL1_GDWB_OGAM_RAMB_END_CNTL2_GDWB_OGAM_RAMB_END_CNTL1_RDWB_OGAM_RAMB_END_CNTL2_RDWB_OGAM_RAMB_OFFSET_BDWB_OGAM_RAMB_OFFSET_GDWB_OGAM_RAMB_OFFSET_RDWB_OGAM_RAMB_REGION_0_1DWB_OGAM_RAMB_REGION_2_3DWB_OGAM_RAMB_REGION_4_5DWB_OGAM_RAMB_REGION_6_7DWB_OGAM_RAMB_REGION_8_9DWB_OGAM_RAMB_REGION_10_11DWB_OGAM_RAMB_REGION_12_13DWB_OGAM_RAMB_REGION_14_15DWB_OGAM_RAMB_REGION_16_17DWB_OGAM_RAMB_REGION_18_19DWB_OGAM_RAMB_REGION_20_21DWB_OGAM_RAMB_REGION_22_23DWB_OGAM_RAMB_REGION_24_25DWB_OGAM_RAMB_REGION_26_27DWB_OGAM_RAMB_REGION_28_29DWB_OGAM_RAMB_REGION_30_31DWB_OGAM_RAMB_REGION_32_33dcn30_dwbc_maskDWB_ENABLEDISPCLK_R_DWB_GATE_DISDISPCLK_G_DWB_GATE_DISDWB_TEST_CLK_SELDWBSCL_LUT_MEM_PWR_FORCEDWBSCL_LUT_MEM_PWR_DISDWBSCL_LUT_MEM_PWR_STATEDWBSCL_LB_MEM_PWR_FORCEDWBSCL_LB_MEM_PWR_DISDWBSCL_LB_MEM_PWR_STATEDWB_OGAM_LUT_MEM_PWR_FORCEDWB_OGAM_LUT_MEM_PWR_DISDWB_OGAM_LUT_MEM_PWR_STATEFC_FRAME_CAPTURE_ENFC_FRAME_CAPTURE_RATEFC_WINDOW_CROP_ENFC_EYE_SELECTIONFC_STEREO_EYE_POLARITYFC_NEW_CONTENTFC_FI_ENFC_FI_PHASEFC_FRAME_CAPTURE_EN_CURRENTFC_FIRST_PIXEL_DELAY_COUNTFC_WINDOW_START_XFC_WINDOW_START_YFC_WINDOW_WIDTHFC_WINDOW_HEIGHTFC_SOURCE_WIDTHFC_SOURCE_HEIGHTDWB_UPDATE_LOCKDWB_UPDATE_PENDINGDWB_CRC_ENDWB_CRC_CONT_ENDWB_CRC_SRC_SELDWB_CRC_RED_MASKDWB_CRC_GREEN_MASKDWB_CRC_BLUE_MASKDWB_CRC_A_MASKDWB_CRC_SIG_REDDWB_CRC_SIG_GREENDWB_CRC_SIG_BLUEDWB_CRC_SIG_AOUT_FORMATOUT_DENORMOUT_MAXOUT_MINDWB_MMHUBBUB_MAX_BACKPRESSUREDWB_HOST_READ_RATE_CONTROLDWBSCL_DATA_OVERFLOW_FLAGDWBSCL_DATA_OVERFLOW_ACKDWBSCL_DATA_OVERFLOW_MASKDWBSCL_DATA_OVERFLOW_INT_STATUSDWBSCL_DATA_OVERFLOW_INT_TYPEDWBSCL_DATA_OVERFLOW_TYPEDWBSCL_DATA_OVERFLOW_OUT_X_CNTDWBSCL_DATA_OVERFLOW_OUT_Y_CNTDWBSCL_COEF_RAM_TAP_PAIR_IDXDWBSCL_COEF_RAM_PHASEDWBSCL_COEF_RAM_FILTER_TYPEDWBSCL_COEF_RAM_SELECT_RDDWBSCL_COEF_RAM_EVEN_TAP_COEFDWBSCL_COEF_RAM_EVEN_TAP_COEF_ENDWBSCL_COEF_RAM_ODD_TAP_COEFDWBSCL_COEF_RAM_ODD_TAP_COEF_ENDWBSCL_COEF_RAM_SELECTDWBSCL_COEF_RAM_SELECT_CURRENTDWBSCL_H_NUM_OF_TAPSDWBSCL_V_NUM_OF_TAPSDWBSCL_H_SCALE_RATIODWBSCL_H_INIT_FRACDWBSCL_H_INIT_INTDWBSCL_V_SCALE_RATIODWBSCL_V_INIT_FRACDWBSCL_V_INIT_INTDWBSCL_BOUNDARY_MODEDWBSCL_BLACK_COLOR_RGBDWBSCL_DEST_WIDTHDWBSCL_DEST_HEIGHTDWB_GAMUT_REMAP_MODE_CURRENTDWB_GAMUT_REMAPA_C11DWB_GAMUT_REMAPA_C12DWB_GAMUT_REMAPA_C13DWB_GAMUT_REMAPA_C14DWB_GAMUT_REMAPA_C21DWB_GAMUT_REMAPA_C22DWB_GAMUT_REMAPA_C23DWB_GAMUT_REMAPA_C24DWB_GAMUT_REMAPA_C31DWB_GAMUT_REMAPA_C32DWB_GAMUT_REMAPA_C33DWB_GAMUT_REMAPA_C34DWB_GAMUT_REMAPB_C11DWB_GAMUT_REMAPB_C12DWB_GAMUT_REMAPB_C13DWB_GAMUT_REMAPB_C14DWB_GAMUT_REMAPB_C21DWB_GAMUT_REMAPB_C22DWB_GAMUT_REMAPB_C23DWB_GAMUT_REMAPB_C24DWB_GAMUT_REMAPB_C31DWB_GAMUT_REMAPB_C32DWB_GAMUT_REMAPB_C33DWB_GAMUT_REMAPB_C34DWB_OGAM_MODEDWB_OGAM_SELECTDWB_OGAM_PWL_DISABLEDWB_OGAM_MODE_CURRENTDWB_OGAM_SELECT_CURRENTDWB_OGAM_LUT_WRITE_COLOR_MASKDWB_OGAM_LUT_READ_COLOR_SELDWB_OGAM_LUT_HOST_SELDWB_OGAM_LUT_CONFIG_MODEDWB_OGAM_LUT_STATUSDWB_OGAM_RAMA_EXP_REGION_START_BDWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_BDWB_OGAM_RAMA_EXP_REGION_START_GDWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_GDWB_OGAM_RAMA_EXP_REGION_START_RDWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_RDWB_OGAM_RAMA_EXP_REGION_START_BASE_BDWB_OGAM_RAMA_EXP_REGION_START_SLOPE_BDWB_OGAM_RAMA_EXP_REGION_START_BASE_GDWB_OGAM_RAMA_EXP_REGION_START_SLOPE_GDWB_OGAM_RAMA_EXP_REGION_START_BASE_RDWB_OGAM_RAMA_EXP_REGION_START_SLOPE_RDWB_OGAM_RAMA_EXP_REGION_END_BASE_BDWB_OGAM_RAMA_EXP_REGION_END_BDWB_OGAM_RAMA_EXP_REGION_END_SLOPE_BDWB_OGAM_RAMA_EXP_REGION_END_BASE_GDWB_OGAM_RAMA_EXP_REGION_END_GDWB_OGAM_RAMA_EXP_REGION_END_SLOPE_GDWB_OGAM_RAMA_EXP_REGION_END_BASE_RDWB_OGAM_RAMA_EXP_REGION_END_RDWB_OGAM_RAMA_EXP_REGION_END_SLOPE_RDWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSETDWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTSDWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSETDWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTSDWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSETDWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTSDWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSETDWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTSDWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSETDWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTSDWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSETDWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTSDWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSETDWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTSDWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSETDWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTSDWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSETDWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTSDWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSETDWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTSDWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSETDWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTSDWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSETDWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTSDWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSETDWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTSDWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSETDWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTSDWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSETDWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTSDWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSETDWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTSDWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSETDWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTSDWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSETDWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTSDWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSETDWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTSDWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSETDWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTSDWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSETDWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTSDWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSETDWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTSDWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSETDWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTSDWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSETDWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTSDWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSETDWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTSDWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSETDWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTSDWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSETDWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTSDWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSETDWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTSDWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSETDWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTSDWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSETDWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTSDWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSETDWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTSDWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSETDWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTSDWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSETDWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTSDWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSETDWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTSDWB_OGAM_RAMB_EXP_REGION_START_BDWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_BDWB_OGAM_RAMB_EXP_REGION_START_GDWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_GDWB_OGAM_RAMB_EXP_REGION_START_RDWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_RDWB_OGAM_RAMB_EXP_REGION_START_BASE_BDWB_OGAM_RAMB_EXP_REGION_START_SLOPE_BDWB_OGAM_RAMB_EXP_REGION_START_BASE_GDWB_OGAM_RAMB_EXP_REGION_START_SLOPE_GDWB_OGAM_RAMB_EXP_REGION_START_BASE_RDWB_OGAM_RAMB_EXP_REGION_START_SLOPE_RDWB_OGAM_RAMB_EXP_REGION_END_BASE_BDWB_OGAM_RAMB_EXP_REGION_END_BDWB_OGAM_RAMB_EXP_REGION_END_SLOPE_BDWB_OGAM_RAMB_EXP_REGION_END_BASE_GDWB_OGAM_RAMB_EXP_REGION_END_GDWB_OGAM_RAMB_EXP_REGION_END_SLOPE_GDWB_OGAM_RAMB_EXP_REGION_END_BASE_RDWB_OGAM_RAMB_EXP_REGION_END_RDWB_OGAM_RAMB_EXP_REGION_END_SLOPE_RDWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSETDWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTSDWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSETDWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTSDWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSETDWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTSDWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSETDWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTSDWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSETDWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTSDWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSETDWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTSDWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSETDWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTSDWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSETDWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTSDWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSETDWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTSDWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSETDWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTSDWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSETDWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTSDWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSETDWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTSDWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSETDWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTSDWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSETDWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTSDWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSETDWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTSDWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSETDWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTSDWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSETDWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTSDWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSETDWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTSDWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSETDWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTSDWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSETDWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTSDWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSETDWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTSDWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSETDWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTSDWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSETDWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTSDWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSETDWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTSDWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSETDWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTSDWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSETDWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTSDWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSETDWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTSDWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSETDWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTSDWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSETDWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTSDWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSETDWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTSDWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSETDWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTSDWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSETDWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTSDWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSETDWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTSDWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSETDWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTSdcn30_dwbc_shiftdcn30_dwbcdwbc_regsdwbc_shiftdwbc_maskdcn30_mmhubbub_registersMCIF_WB_BUFMGR_SW_CONTROLMCIF_WB_BUFMGR_CUR_LINE_RMCIF_WB_BUFMGR_STATUSMCIF_WB_BUF_PITCHMCIF_WB_BUF_1_STATUSMCIF_WB_BUF_1_STATUS2MCIF_WB_BUF_2_STATUSMCIF_WB_BUF_2_STATUS2MCIF_WB_BUF_3_STATUSMCIF_WB_BUF_3_STATUS2MCIF_WB_BUF_4_STATUSMCIF_WB_BUF_4_STATUS2MCIF_WB_ARBITRATION_CONTROLMCIF_WB_SCLK_CHANGEMCIF_WB_TEST_DEBUG_INDEXMCIF_WB_TEST_DEBUG_DATAMCIF_WB_BUF_1_ADDR_YMCIF_WB_BUF_1_ADDR_Y_OFFSETMCIF_WB_BUF_1_ADDR_CMCIF_WB_BUF_1_ADDR_C_OFFSETMCIF_WB_BUF_2_ADDR_YMCIF_WB_BUF_2_ADDR_Y_OFFSETMCIF_WB_BUF_2_ADDR_CMCIF_WB_BUF_2_ADDR_C_OFFSETMCIF_WB_BUF_3_ADDR_YMCIF_WB_BUF_3_ADDR_Y_OFFSETMCIF_WB_BUF_3_ADDR_CMCIF_WB_BUF_3_ADDR_C_OFFSETMCIF_WB_BUF_4_ADDR_YMCIF_WB_BUF_4_ADDR_Y_OFFSETMCIF_WB_BUF_4_ADDR_CMCIF_WB_BUF_4_ADDR_C_OFFSETMCIF_WB_BUFMGR_VCE_CONTROLMCIF_WB_NB_PSTATE_LATENCY_WATERMARKMCIF_WB_NB_PSTATE_CONTROLMCIF_WB_WATERMARKMCIF_WB_CLOCK_GATER_CONTROLMCIF_WB_WARM_UP_CNTLMCIF_WB_SELF_REFRESH_CONTROLMULTI_LEVEL_QOS_CTRLMCIF_WB_SECURITY_LEVELMCIF_WB_BUF_LUMA_SIZEMCIF_WB_BUF_CHROMA_SIZEMCIF_WB_BUF_1_ADDR_Y_HIGHMCIF_WB_BUF_1_ADDR_C_HIGHMCIF_WB_BUF_2_ADDR_Y_HIGHMCIF_WB_BUF_2_ADDR_C_HIGHMCIF_WB_BUF_3_ADDR_Y_HIGHMCIF_WB_BUF_3_ADDR_C_HIGHMCIF_WB_BUF_4_ADDR_Y_HIGHMCIF_WB_BUF_4_ADDR_C_HIGHMCIF_WB_BUF_1_RESOLUTIONMCIF_WB_BUF_2_RESOLUTIONMCIF_WB_BUF_3_RESOLUTIONMCIF_WB_BUF_4_RESOLUTIONSMU_WM_CONTROLMMHUBBUB_WARMUP_ADDR_REGIONMMHUBBUB_WARMUP_BASE_ADDR_HIGHMMHUBBUB_WARMUP_BASE_ADDR_LOWMMHUBBUB_WARMUP_CONTROL_STATUSMMHUBBUB_WARMUP_P_VMIDMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBIdcn30_mmhubbub_maskMCIF_WB_BUFMGR_ENABLEMCIF_WB_BUFMGR_SW_INT_ENMCIF_WB_BUFMGR_SW_INT_ACKMCIF_WB_BUFMGR_SW_SLICE_INT_ENMCIF_WB_BUFMGR_SW_OVERRUN_INT_ENMCIF_WB_BUFMGR_SW_LOCKMCIF_WB_P_VMIDMCIF_WB_BUF_ADDR_FENCE_ENMCIF_WB_BUFMGR_VCE_INT_STATUSMCIF_WB_BUFMGR_SW_INT_STATUSMCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUSMCIF_WB_BUFMGR_CUR_BUFMCIF_WB_BUFMGR_BUFTAGMCIF_WB_BUFMGR_CUR_LINE_LMCIF_WB_BUFMGR_NEXT_BUFMCIF_WB_BUF_LUMA_PITCHMCIF_WB_BUF_CHROMA_PITCHMCIF_WB_BUF_1_ACTIVEMCIF_WB_BUF_1_SW_LOCKEDMCIF_WB_BUF_1_VCE_LOCKEDMCIF_WB_BUF_1_OVERFLOWMCIF_WB_BUF_1_DISABLEMCIF_WB_BUF_1_MODEMCIF_WB_BUF_1_BUFTAGMCIF_WB_BUF_1_NXT_BUFMCIF_WB_BUF_1_FIELDMCIF_WB_BUF_1_CUR_LINE_LMCIF_WB_BUF_1_LONG_LINE_ERRORMCIF_WB_BUF_1_SHORT_LINE_ERRORMCIF_WB_BUF_1_FRAME_LENGTH_ERRORMCIF_WB_BUF_1_CUR_LINE_RMCIF_WB_BUF_1_NEW_CONTENTMCIF_WB_BUF_1_COLOR_DEPTHMCIF_WB_BUF_1_TMZ_BLACK_PIXELMCIF_WB_BUF_1_TMZMCIF_WB_BUF_1_Y_OVERRUNMCIF_WB_BUF_1_C_OVERRUNMCIF_WB_BUF_2_ACTIVEMCIF_WB_BUF_2_SW_LOCKEDMCIF_WB_BUF_2_VCE_LOCKEDMCIF_WB_BUF_2_OVERFLOWMCIF_WB_BUF_2_DISABLEMCIF_WB_BUF_2_MODEMCIF_WB_BUF_2_BUFTAGMCIF_WB_BUF_2_NXT_BUFMCIF_WB_BUF_2_FIELDMCIF_WB_BUF_2_CUR_LINE_LMCIF_WB_BUF_2_LONG_LINE_ERRORMCIF_WB_BUF_2_SHORT_LINE_ERRORMCIF_WB_BUF_2_FRAME_LENGTH_ERRORMCIF_WB_BUF_2_CUR_LINE_RMCIF_WB_BUF_2_NEW_CONTENTMCIF_WB_BUF_2_COLOR_DEPTHMCIF_WB_BUF_2_TMZ_BLACK_PIXELMCIF_WB_BUF_2_TMZMCIF_WB_BUF_2_Y_OVERRUNMCIF_WB_BUF_2_C_OVERRUNMCIF_WB_BUF_3_ACTIVEMCIF_WB_BUF_3_SW_LOCKEDMCIF_WB_BUF_3_VCE_LOCKEDMCIF_WB_BUF_3_OVERFLOWMCIF_WB_BUF_3_DISABLEMCIF_WB_BUF_3_MODEMCIF_WB_BUF_3_BUFTAGMCIF_WB_BUF_3_NXT_BUFMCIF_WB_BUF_3_FIELDMCIF_WB_BUF_3_CUR_LINE_LMCIF_WB_BUF_3_LONG_LINE_ERRORMCIF_WB_BUF_3_SHORT_LINE_ERRORMCIF_WB_BUF_3_FRAME_LENGTH_ERRORMCIF_WB_BUF_3_CUR_LINE_RMCIF_WB_BUF_3_NEW_CONTENTMCIF_WB_BUF_3_COLOR_DEPTHMCIF_WB_BUF_3_TMZ_BLACK_PIXELMCIF_WB_BUF_3_TMZMCIF_WB_BUF_3_Y_OVERRUNMCIF_WB_BUF_3_C_OVERRUNMCIF_WB_BUF_4_ACTIVEMCIF_WB_BUF_4_SW_LOCKEDMCIF_WB_BUF_4_VCE_LOCKEDMCIF_WB_BUF_4_OVERFLOWMCIF_WB_BUF_4_DISABLEMCIF_WB_BUF_4_MODEMCIF_WB_BUF_4_BUFTAGMCIF_WB_BUF_4_NXT_BUFMCIF_WB_BUF_4_FIELDMCIF_WB_BUF_4_CUR_LINE_LMCIF_WB_BUF_4_LONG_LINE_ERRORMCIF_WB_BUF_4_SHORT_LINE_ERRORMCIF_WB_BUF_4_FRAME_LENGTH_ERRORMCIF_WB_BUF_4_CUR_LINE_RMCIF_WB_BUF_4_NEW_CONTENTMCIF_WB_BUF_4_COLOR_DEPTHMCIF_WB_BUF_4_TMZ_BLACK_PIXELMCIF_WB_BUF_4_TMZMCIF_WB_BUF_4_Y_OVERRUNMCIF_WB_BUF_4_C_OVERRUNMCIF_WB_CLIENT_ARBITRATION_SLICEMCIF_WB_TIME_PER_PIXELWM_CHANGE_ACK_FORCE_ONMCIF_WB_CLI_WATERMARK_MASKMCIF_WB_BUFMGR_VCE_LOCK_IGNOREMCIF_WB_BUFMGR_VCE_INT_ENMCIF_WB_BUFMGR_VCE_INT_ACKMCIF_WB_BUFMGR_VCE_SLICE_INT_ENMCIF_WB_BUFMGR_VCE_LOCKMCIF_WB_BUFMGR_SLICE_SIZENB_PSTATE_CHANGE_REFRESH_WATERMARKNB_PSTATE_CHANGE_FORCE_ONNB_PSTATE_ALLOW_FOR_URGENTMCIF_WB_CLI_WATERMARKMCIF_WB_CLI_CLOCK_GATER_OVERRIDEMCIF_WB_PITCH_SIZE_WARMUPDIS_REFRESH_UNDER_NBPREQPERFRAME_SELF_REFRESHMAX_SCALED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LKChangeLatencyMarginUSRRetrainingLatencyMarginSynchronizedSurfacesEffectiveLBLatencyHidingYEffectiveLBLatencyHidingCWritebackDRAMClockChangeLatencyMarginWritebackFCLKChangeLatencyMarginWritebackLatencyHidingTotalPixelBWEffectiveDETBufferSizeYActiveClockChangeLatencyHidingYActiveClockChangeLatencyHidingCActiveClockChangeLatencyHidingFoundCriticalSurfaceLastSurfaceWithoutMarginFCLKChangeSupportNumberDRAMClockChangeMethodDRAMClockChangeSupportNumberdst_y_pstatesrc_y_pstate_lsrc_y_pstate_csrc_y_ahead_lsrc_y_ahead_csub_vp_lines_lsub_vp_lines_cCalculateVMRowAndSwath_locals_stPDEAndMetaPTEBytesFrameYPDEAndMetaPTEBytesFrameCMetaRowByteYMetaRowByteCPixelPTEBytesPerRowYPixelPTEBytesPerRowCPixelPTEBytesPerRowStorageYPixelPTEBytesPerRowStorageCPixelPTEBytesPerRowY_one_row_per_framePixelPTEBytesPerRowC_one_row_per_framedpte_row_width_luma_ub_one_row_per_framedpte_row_height_luma_one_row_per_framedpte_row_width_chroma_ub_one_row_per_framedpte_row_height_chroma_one_row_per_frameone_row_per_frame_fits_in_bufferHostVMDynamicLevelsUseMinimumDCFCLK_locals_stNormalEfficiencyTotalMaxPrefetchFlipDPTERowBandwidthPixelDCFCLKCyclesRequiredInPrefetchPrefetchPixelLinesTimeDCFCLKRequiredForPeakBandwidthPerSurfaceDynamicMetadataVMExtraLatencyMinimumTWaitDPTEBandwidthDCFCLKRequiredForAverageBandwidthExtraLatencyBytesExtraLatencyCyclesDCFCLKRequiredForPeakBandwidthNoOfDPPStateMinimumTvmPlus2Tr0CalculatePrefetchSchedule_locals_stMyErrorDPPCyclesDISPCLKCyclesDSTTotalPixelsAfterScalerLineTimedst_y_prefetch_equprefetch_bw_otoTvm_otoTr0_otoTvm_oto_linesTr0_oto_linesdst_y_prefetch_otoTimeForFetchingMetaPTETimeForFetchingRowInVBlankLinesToRequestPrefetchPixelDataHostVMDynamicLevelsTripstrip_to_memTvm_tripsTr0_tripsTvm_trips_roundedTr0_trips_roundedmax_TswLsw_otoTpre_roundedprefetch_bw_equTvm_equTr0_equTdmbfTdmecTdmsksprefetch_sw_bytesprefetch_bw_prbytes_ppdep_bytesmin_Lsw_otoTsw_est1Tsw_est3PrefetchBandwidth1PrefetchBandwidth2PrefetchBandwidth3PrefetchBandwidth4display_mode_lib_scratch_stdml_core_mode_support_localsdml_core_mode_programming_localsCalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_localsCalculateVMRowAndSwath_localsUseMinimumDCFCLK_localsCalculatePrefetchSchedule_localsCalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_paramsCalculateVMRowAndSwath_paramsUseMinimumDCFCLK_paramsCalculateSwathAndDETConfiguration_paramsCalculateStutterEfficiency_paramsCalculatePrefetchSchedule_paramsdisplay_mode_lib_stdml_display_rq_regs_st_vcs_dpi_dml_display_rq_regs_stdml_display_dlg_regs_st_vcs_dpi_dml_display_dlg_regs_stdml_display_ttu_regs_st_vcs_dpi_dml_display_ttu_regs_stdml_display_arb_params_st_vcs_dpi_dml_display_arb_params_stmax_req_outstandingmin_req_outstandingsat_level_ushvm_max_qos_commit_thresholdhvm_min_req_outstand_commit_thresholdcompbuf_reserved_space_kbytesdml_display_plane_rq_regs_st_vcs_dpi_dml_display_plane_rq_regs_sttest_pattern_dyn_rangeTEST_PATTERN_DYN_RANGE_VESATEST_PATTERN_DYN_RANGE_CEAtest_pattern_modeTEST_PATTERN_MODE_COLORSQUARES_RGBTEST_PATTERN_MODE_COLORSQUARES_YCBCR601TEST_PATTERN_MODE_COLORSQUARES_YCBCR709TEST_PATTERN_MODE_VERTICALBARSTEST_PATTERN_MODE_HORIZONTALBARSTEST_PATTERN_MODE_SINGLERAMP_RGBTEST_PATTERN_MODE_DUALRAMP_RGBTEST_PATTERN_MODE_XR_BIAS_RGBtest_pattern_color_formatTEST_PATTERN_COLOR_FORMAT_BPC_6TEST_PATTERN_COLOR_FORMAT_BPC_8TEST_PATTERN_COLOR_FORMAT_BPC_10TEST_PATTERN_COLOR_FORMAT_BPC_12trigger_source_selectTRIGGER_SOURCE_SELECT_LOGIC_ZEROTRIGGER_SOURCE_SELECT_CRTC_VSYNCATRIGGER_SOURCE_SELECT_CRTC_HSYNCATRIGGER_SOURCE_SELECT_CRTC_VSYNCBTRIGGER_SOURCE_SELECT_CRTC_HSYNCBTRIGGER_SOURCE_SELECT_GENERICFTRIGGER_SOURCE_SELECT_GENERICETRIGGER_SOURCE_SELECT_VSYNCATRIGGER_SOURCE_SELECT_HSYNCATRIGGER_SOURCE_SELECT_VSYNCBTRIGGER_SOURCE_SELECT_HSYNCBTRIGGER_SOURCE_SELECT_HPD1TRIGGER_SOURCE_SELECT_HPD2TRIGGER_SOURCE_SELECT_GENERICDTRIGGER_SOURCE_SELECT_GENERICCTRIGGER_SOURCE_SELECT_VIDEO_CAPTURETRIGGER_SOURCE_SELECT_GSL_GROUP0TRIGGER_SOURCE_SELECT_GSL_GROUP1TRIGGER_SOURCE_SELECT_GSL_GROUP2TRIGGER_SOURCE_SELECT_BLONYTRIGGER_SOURCE_SELECT_GENERICATRIGGER_SOURCE_SELECT_GENERICBTRIGGER_SOURCE_SELECT_GSL_ALLOW_FLIPTRIGGER_SOURCE_SELECT_MANUAL_TRIGGERtrigger_polarity_selectTRIGGER_POLARITY_SELECT_LOGIC_ZEROTRIGGER_POLARITY_SELECT_CRTCTRIGGER_POLARITY_SELECT_GENERICATRIGGER_POLARITY_SELECT_GENERICBTRIGGER_POLARITY_SELECT_HSYNCATRIGGER_POLARITY_SELECT_HSYNCBTRIGGER_POLARITY_SELECT_VIDEO_CAPTURETRIGGER_POLARITY_SELECT_GENERICCfbc_hw_max_resolution_supportedFBC_MAX_XFBC_MAX_YFBC_MAX_X_SGFBC_MAX_Y_SGdce110_compressor_reg_offsetsdcp_offsetdmif_offsetdce110_compressorcsc_color_modeCSC_COLOR_MODE_GRAPHICS_BYPASSCSC_COLOR_MODE_GRAPHICS_PREDEFINEDCSC_COLOR_MODE_GRAPHICS_OUTPUT_CSCgrph_color_adjust_optionGRPH_COLOR_MATRIX_HW_DEFAULTGRPH_COLOR_MATRIX_SWinput_csc_matrixhdcp_message_idHDCP_MESSAGE_ID_INVALIDHDCP_MESSAGE_ID_READ_BKSVHDCP_MESSAGE_ID_READ_RI_R0HDCP_MESSAGE_ID_READ_PJHDCP_MESSAGE_ID_WRITE_AKSVHDCP_MESSAGE_ID_WRITE_AINFOHDCP_MESSAGE_ID_WRITE_ANHDCP_MESSAGE_ID_READ_VH_XHDCP_MESSAGE_ID_READ_VH_0HDCP_MESSAGE_ID_READ_VH_1HDCP_MESSAGE_ID_READ_VH_2HDCP_MESSAGE_ID_READ_VH_3HDCP_MESSAGE_ID_READ_VH_4HDCP_MESSAGE_ID_READ_BCAPSHDCP_MESSAGE_ID_READ_BSTATUSHDCP_MESSAGE_ID_READ_KSV_FIFOHDCP_MESSAGE_ID_READ_BINFOHDCP_MESSAGE_ID_HDCP2VERSIONHDCP_MESSAGE_ID_RX_CAPSHDCP_MESSAGE_ID_WRITE_AKE_INITHDCP_MESSAGE_ID_READ_AKE_SEND_CERTHDCP_MESSAGE_ID_WRITE_AKE_NO_STORED_KMHDCP_MESSAGE_ID_WRITE_AKE_STORED_KMHDCP_MESSAGE_ID_READ_AKE_SEND_H_PRIMEHDCP_MESSAGE_ID_READ_AKE_SEND_PAIRING_INFOHDCP_MESSAGE_ID_WRITE_LC_INITHDCP_MESSAGE_ID_READ_LC_SEND_L_PRIMEHDCP_MESSAGE_ID_WRITE_SKE_SEND_EKSHDCP_MESSAGE_ID_READ_REPEATER_AUTH_SEND_RECEIVERID_LISTHDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_SEND_ACKHDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_STREAM_MANAGEHDCP_MESSAGE_ID_READ_REPEATER_AUTH_STREAM_READYHDCP_MESSAGE_ID_READ_RXSTATUSHDCP_MESSAGE_ID_WRITE_CONTENT_STREAM_TYPEHDCP_MESSAGE_ID_WRITE_PS175_CMDHDCP_MESSAGE_ID_READ_PS175_RSPHDCP_MESSAGE_ID_MAXhdcp_versionHDCP_UnknownHDCP_VERSION_14HDCP_VERSION_22hdcp_linkHDCP_LINK_PRIMARYHDCP_LINK_SECONDARYhdcp_message_statusHDCP_MESSAGE_SUCCESSHDCP_MESSAGE_FAILUREHDCP_MESSAGE_UNSUPPORTEDhdcp_protection_messagemsg_idprotection_propertiesprocess_transactionblack_color_formatBLACK_COLOR_FORMAT_RGB_FULLRANGEBLACK_COLOR_FORMAT_RGB_LIMITEDBLACK_COLOR_FORMAT_YUV_TVBLACK_COLOR_FORMAT_YUV_CVBLACK_COLOR_FORMAT_YUV_SUPER_AABLACK_COLOR_FORMAT_DEBUGdc_color_space_typeCOLOR_SPACE_RGB_TYPECOLOR_SPACE_RGB_LIMITED_TYPECOLOR_SPACE_YCBCR601_TYPECOLOR_SPACE_YCBCR709_TYPECOLOR_SPACE_YCBCR2020_TYPECOLOR_SPACE_YCBCR601_LIMITED_TYPECOLOR_SPACE_YCBCR709_LIMITED_TYPECOLOR_SPACE_YCBCR709_BLACK_TYPEout_csc_color_matrix_typecolor_space_typedc_reg_value_masksgamma_pixelchannel_nameCHANNEL_NAME_REDCHANNEL_NAME_GREENCHANNEL_NAME_BLUEhw_x_pointregamma_y_redregamma_y_greenregamma_y_bluepwl_float_data_exdelta_rdelta_gdelta_bhw_point_positionHW_POINT_POSITION_MIDDLEHW_POINT_POSITION_LEFTHW_POINT_POSITION_RIGHTgamma_pointleft_indexright_indexcoeffpixel_gamma_pointgamma_coefficientsuser_gammauser_contrastuser_brightnesspwl_float_datatable_typetype_pq_tabletype_de_pq_tablegammaRampArraygammaFromEdidgammaFromEdidExgammaFromUsercoeffFromUsercoeffFromEdidapplyDegammagammaPredefinedSRGBgammaPredefinedPQgammaPredefinedPQ2084InterimgammaPredefined36gammaPredefinedResetregamma_flagsregamma_rampregamma_coeffA0A1A2A3regamma_luthdr_tm_paramsmin_contentmax_contentmin_displaymax_displayskip_tmcalculate_bufferbuffer_indexgamma_of_2translate_from_linear_space_argscal_bufferdividersdivider1divider2divider3dmub_out_cmd_typeDMUB_OUT_CMD__NULLDMUB_OUT_CMD__DP_AUX_REPLYDMUB_OUT_CMD__DP_HPD_NOTIFYDMUB_OUT_CMD__SET_CONFIG_REPLYDMUB_OUT_CMD__DPIA_NOTIFICATIONaux_reply_control_datadmub_rb_cmd_dp_aux_replydp_hpd_typeDP_HPDDP_IRQdp_hpd_datahpd_typedmub_rb_cmd_dp_hpd_notifyset_config_reply_control_datadmub_rb_cmd_dp_set_config_replyset_config_reply_controldmub_rb_out_cmddp_aux_replydp_hpd_notifyset_config_replydpia_notify_bw_alloc_statusDPIA_BW_REQ_FAILEDDPIA_BW_REQ_SUCCESSDPIA_EST_BW_CHANGEDDPIA_BW_ALLOC_CAPS_CHANGEDdmub_gpint_commandDMUB_GPINT__INVALID_COMMANDDMUB_GPINT__GET_FW_VERSIONDMUB_GPINT__STOP_FWDMUB_GPINT__GET_PSR_STATEDMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASKDMUB_GPINT__PSR_RESIDENCYDMUB_GPINT__NOTIFY_DETECTION_DONEDMUB_GPINT__GET_REPLAY_STATEDMUB_GPINT__REPLAY_RESIDENCYDMUB_GPINT__UPDATE_TRACE_BUFFER_MASKDMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD1DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD2DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD3DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITYdmub_srv_common_reg_offsetDMCUB_CNTLDMCUB_MEM_CNTLDMCUB_SEC_CNTLDMCUB_INBOX0_SIZEDMCUB_INBOX0_RPTRDMCUB_INBOX0_WPTRDMCUB_INBOX1_BASE_ADDRESSDMCUB_INBOX1_SIZEDMCUB_INBOX1_RPTRDMCUB_INBOX1_WPTRDMCUB_OUTBOX0_BASE_ADDRESSDMCUB_OUTBOX0_SIZEDMCUB_OUTBOX0_RPTRDMCUB_OUTBOX0_WPTRDMCUB_OUTBOX1_BASE_ADDRESSDMCUB_OUTBOX1_SIZEDMCUB_OUTBOX1_RPTRDMCUB_OUTBOX1_WPTRDMCUB_REGION3_CW0_OFFSETDMCUB_REGION3_CW1_OFFSETDMCUB_REGION3_CW2_OFFSETDMCUB_REGION3_CW3_OFFSETDMCUB_REGION3_CW4_OFFSETDMCUB_REGION3_CW5_OFFSETDMCUB_REGION3_CW6_OFFSETDMCUB_REGION3_CW7_OFFSETDMCUB_REGION3_CW0_OFFSET_HIGHDMCUB_REGION3_CW1_OFFSET_HIGHDMCUB_REGION3_CW2_OFFSET_HIGHDMCUB_REGION3_CW3_OFFSET_HIGHDMCUB_REGION3_CW4_OFFSET_HIGHDMCUB_REGION3_CW5_OFFSET_HIGHDMCUB_REGION3_CW6_OFFSET_HIGHDMCUB_REGION3_CW7_OFFSET_HIGHDMCUB_REGION3_CW0_BASE_ADDRESSDMCUB_REGION3_CW1_BASE_ADDRESSDMCUB_REGION3_CW2_BASE_ADDRESSDMCUB_REGION3_CW3_BASE_ADDRESSDMCUB_REGION3_CW4_BASE_ADDRESSDMCUB_REGION3_CW5_BASE_ADDRESSDMCUB_REGION3_CW6_BASE_ADDRESSDMCUB_REGION3_CW7_BASE_ADDRESSDMCUB_REGION3_CW0_TOP_ADDRESSDMCUB_REGION3_CW1_TOP_ADDRESSDMCUB_REGION3_CW2_TOP_ADDRESSDMCUB_REGION3_CW3_TOP_ADDRESSDMCUB_REGION3_CW4_TOP_ADDRESSDMCUB_REGION3_CW5_TOP_ADDRESSDMCUB_REGION3_CW6_TOP_ADDRESSDMCUB_REGION3_CW7_TOP_ADDRESSDMCUB_REGION4_OFFSETDMCUB_REGION4_OFFSET_HIGHDMCUB_REGION4_TOP_ADDRESSDMCUB_REGION5_OFFSETDMCUB_REGION5_OFFSET_HIGHDMC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_atom_execute_table_lockedamdgpu_atom_parsefrevcrevamdgpu_atom_parse_cmd_headeramdgpu_atom_parse_data_headeramdgpu_atombios_allocate_fb_scratchto_leamdgpu_atombios_copy_swapamdgpu_atombios_finiamdgpu_atombios_get_asic_ss_infostrobe_modeamdgpu_atombios_get_clock_dividersamdgpu_atombios_get_clock_infoamdgpu_atombios_get_connector_info_from_object_tableamdgpu_atombios_get_data_tableamdgpu_atombios_get_default_voltagesamdgpu_atombios_get_gfx_infoamdgpu_atombios_get_igp_ss_overridesleakage_idxamdgpu_atombios_get_leakage_vddc_based_on_leakage_idxamdgpu_atombios_get_max_vddcmpll_paramamdgpu_atombios_get_memory_pll_dividerssvd_gpio_idsvc_gpio_idamdgpu_atombios_get_svi2_infoamdgpu_atombios_get_vbios_versionvoltage_tableamdgpu_atombios_get_voltage_tableamdgpu_atombios_get_vram_widthamdgpu_atombios_has_dce_engine_infoamdgpu_atombios_has_gpu_virtualization_tableamdgpu_atombios_i2c_initamdgpu_atombios_initmodule_indexreg_tableamdgpu_atombios_init_mc_reg_tableamdgpu_atombios_is_voltage_gpioamdgpu_atombios_lookup_gpioamdgpu_atombios_scratch_need_asic_inithungamdgpu_atombios_scratch_regs_engine_hungamdgpu_atombios_scratch_regs_lockamdgpu_atombios_scratch_regs_set_backlight_leveleng_clockamdgpu_atombios_set_engine_dram_timingsamdgpu_atombios_sysfs_initamdgpu_cs_bo_validateamdgpu_cs_fence_to_handle_ioctlamdgpu_cs_find_mappingmax_vis_bytesamdgpu_cs_get_threshold_for_movesamdgpu_cs_ioctlchunk_ibamdgpu_cs_job_idxamdgpu_cs_p2_dependenciesamdgpu_cs_parser_bosamdgpu_cs_parser_finiamdgpu_cs_pass1amdgpu_cs_pass2amdgpu_cs_patch_ibsnum_vis_bytesamdgpu_cs_report_moved_bytesamdgpu_cs_submitamdgpu_cs_sync_ringsamdgpu_cs_vm_handlingamdgpu_cs_wait_any_fenceamdgpu_cs_wait_fences_ioctlamdgpu_cs_wait_ioctlamdgpu_current_bpc_openamdgpu_current_bpc_showamdgpu_current_colorspace_openamdgpu_current_colorspace_showamdgpu_debugfs_firmware_info_openamdgpu_debugfs_firmware_info_showamdgpu_debugfs_firmware_initamdgpu_debugfs_gem_info_openamdgpu_debugfs_gem_info_showamdgpu_debugfs_gem_initamdgpu_disable_vblank_kmsamdgpu_dm_encoder_destroyamdgpu_dm_hpd_finiamdgpu_dm_hpd_initamdgpu_dm_initialize_dp_connectoramdgpu_dm_irq_finiamdgpu_dm_irq_handleramdgpu_dm_irq_initint_paramshandler_argsamdgpu_dm_irq_register_interruptamdgpu_dm_irq_resume_earlyamdgpu_dm_irq_resume_lateamdgpu_dm_irq_suspendamdgpu_dm_irq_unregister_interruptamdgpu_dm_mst_connector_early_unregisteramdgpu_dm_mst_connector_late_registeramdgpu_dm_outbox_initamdgpu_dm_set_crtc_irq_stateamdgpu_dm_set_dmub_outbox_irq_stateamdgpu_dm_set_dmub_trace_irq_stateamdgpu_dm_set_hpd_irq_stateamdgpu_dm_set_irq_funcsamdgpu_dm_set_pflip_irq_stateamdgpu_dm_set_vline0_irq_stateamdgpu_dm_set_vupdate_irq_stateamdgpu_dm_wb_cleanup_jobamdgpu_dm_wb_connector_get_modeswbconamdgpu_dm_wb_connector_initamdgpu_dm_wb_encoder_atomic_checkamdgpu_dm_wb_prepare_jobamdgpu_dpm_baco_enteramdgpu_dpm_baco_exitamdgpu_dpm_baco_resetamdgpu_dpm_compute_clocksamdgpu_dpm_debugfs_print_current_performance_leveltask_idamdgpu_dpm_dispatch_taskamdgpu_dpm_display_clock_voltage_requestamdgpu_dpm_display_configuration_changedisable_memory_clock_switchamdgpu_dpm_display_disable_memory_clock_switchamdgpu_dpm_emit_clock_levelsamdgpu_dpm_enable_gfx_featuresamdgpu_dpm_enable_jpegamdgpu_dpm_enable_mgpu_fan_boostamdgpu_dpm_enable_uvdamdgpu_dpm_enable_vceamdgpu_dpm_enable_vpeamdgpu_dpm_force_clock_levelamdgpu_dpm_force_performance_levelamdgpu_dpm_get_apu_thermal_limitamdgpu_dpm_get_clock_by_typeamdgpu_dpm_get_clock_by_type_with_latencyamdgpu_dpm_get_clock_by_type_with_voltageamdgpu_dpm_get_current_clocksamdgpu_dpm_get_current_power_stateamdgpu_dpm_get_display_mode_validation_clksclock_tableamdgpu_dpm_get_dpm_clock_tableamdgpu_dpm_get_dpm_freq_rangeamdgpu_dpm_get_ecc_infoamdgpu_dpm_get_entrycount_gfxoffamdgpu_dpm_get_fan_control_modeamdgpu_dpm_get_fan_speed_pwmamdgpu_dpm_get_fan_speed_rpmamdgpu_dpm_get_gpu_metricsmax_clocksamdgpu_dpm_get_max_sustainable_clocks_by_dcamdgpu_dpm_get_mclkamdgpu_dpm_get_mclk_odamdgpu_dpm_get_num_cpu_coresamdgpu_dpm_get_performance_levelpm_metricsamdgpu_dpm_get_pm_metricspp_limit_levelpower_typeamdgpu_dpm_get_power_limitamdgpu_dpm_get_power_profile_modeamdgpu_dpm_get_pp_num_statesamdgpu_dpm_get_pp_tableamdgpu_dpm_get_ppfeature_statusamdgpu_dpm_get_residency_gfxoffamdgpu_dpm_get_sclkamdgpu_dpm_get_sclk_odamdgpu_dpm_get_smu_prv_buf_detailsamdgpu_dpm_get_status_gfxoffamdgpu_dpm_get_thermal_throttling_counterclock_values_in_khzamdgpu_dpm_get_uclk_dpm_statesamdgpu_dpm_get_vce_clock_statemode_descamdgpu_dpm_get_xgmi_plpd_modeamdgpu_dpm_gfx_state_changeamdgpu_dpm_handle_passthrough_sbramdgpu_dpm_is_baco_supportedamdgpu_dpm_is_cclk_dpm_supportedamdgpu_dpm_is_mode1_reset_supportedamdgpu_dpm_is_overdrive_supportedamdgpu_dpm_mode1_resetamdgpu_dpm_mode2_resetamdgpu_dpm_notify_rlc_stateamdgpu_dpm_notify_smu_enable_pweamdgpu_dpm_odn_edit_dpm_tableamdgpu_dpm_print_clock_levelsamdgpu_dpm_read_sensoramdgpu_dpm_send_hbm_bad_channel_flagamdgpu_dpm_send_hbm_bad_pages_numamdgpu_dpm_set_active_display_countamdgpu_dpm_set_apu_thermal_limitamdgpu_dpm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aracteristicsready_to_undockexternal_gpu_informationamdgpu_atifnotification_cfgamdgpu_atcs_functionsget_ext_statepcie_perf_reqpcie_dev_rdypcie_bus_widthpower_shift_controlamdgpu_atcsamdgpu_acpi_privatifatcsatom_smc_dpm_info_v4_9GpioSclGpioSdaFchUsbPdSlaveAddrI2cSpareLedPcieLedErrorLedSpare1PaddingMem1BoardPowerPaddingBACO_SEQUENCEMSR_SEQUENCEBAMACO_SEQUENCEULPS_SEQUENCED3HOT_SEQUENCE_COUNTFsetVdroopPiecewiseLinearDroopInt_tTEMP_EDGETEMP_HOTSPOTTEMP_MEMTEMP_VR_GFXTEMP_VR_MEM0TEMP_VR_MEM1TEMP_VR_SOCTEMP_LIQUID0TEMP_LIQUID1TEMP_PLXTEMP_COUNTTDC_THROTTLER_GFXTDC_THROTTLER_SOCTDC_THROTTLER_COUNTFminFmaxUclkDpmChangeRange_tTdcLimitTauTemperatureLimitTotalPowerPaddingSmnclkDpmFreqSmnclkDpmVoltagePerPartDroopVsetGfxDfllPaddingPerPartDroopSocLIVminPaddingLIVminFreqTableDtbclkPerPartDroopModelGfxDfllFclkBoostFreqFclkParamPaddingGfxclkPaddingGfxGpoSubFeatureMaskGfxGpoEnabledWorkPolicyMaskGfxGpoDisabledWorkPolicyMaskGfxGpoPaddingGfxGpoVotingAllowGfxGpoPadding32GfxDcsFoptGfxDcsFclkFoptGfxDcsUclkFoptDcsGfxOffVoltageDcsMinGfxOffTimeDcsMaxGfxOffTimeDcsMinCreditAccumDcsExitHysteresisDcsTimeoutDcsParamPaddingFlopsPerByteTableUclkDpmPstatesUclkDpmSrcFreqRangeUclkDpmTargFreqRangeUclkDpmMidstepFreqUclkMidstepPaddingFanGainFanPadding16dBtcGbGfxDfllModelSelectPiecewiseLinearDroopIntGfxDfllCustomerVariantVcBtcEnabledVcBtcVminT0VcBtcFixedVminAgingOffsetVcBtcVmin2PsmDegrationGbVcBtcPsmAVcBtcPsmBVcBtcVminAVcBtcVminBLedGpioGfxPowerStagesGpioSkuReservedGamingClkUclkSpreadPaddingHsrEnabledVddqOffEnabledPaddingUmcFlagsSocLIVminoffsetPPTable_beige_goby_tFclkAverageLpfTauVcnClkAverageLpfTaupadding16DriverSmuConfigDriverSmuConfigExternal_tCustomGfxVfCurveCustomCurveFminUclkFminFanLinearPwmPointsFanLinearTempPointsVddGfxOffsetFanZeroRpmStopTempAverageFclkFrequencyPreDsAverageFclkFrequencyPostDsCurrFanPwmD3HotEntryCountPerModeD3HotExitCountPerModeArmMsgReceivedCountPerModeAverageVclk0FrequencyAverageDclk0FrequencyAverageVclk1FrequencyAverageDclk1FrequencyAverageGfxclkFrequencyTargetPadding16_2AccCntThrottlingPercentageSmuMetrics_V2_tVcnUsagePercentage0VcnUsagePercentage1SmuMetrics_V3_tApuSTAPMSmartShiftLimitAverageApuSocketPowerApuSTAPMLimitSmuMetrics_V4_tSmuMetricsSmuMetrics_V2SmuMetrics_V3SmuMetrics_V4SmuMetricsExternal_tFclk_MinFreqStepDpmActivityMonitorCoeffIntDpmActivityMonitorCoeffIntExternal_tSMU_11_0_7_ODFEATURE_CAPSMU_11_0_7_ODCAP_GFXCLK_LIMITSSMU_11_0_7_ODCAP_GFXCLK_CURVESMU_11_0_7_ODCAP_UCLK_LIMITSSMU_11_0_7_ODCAP_POWER_LIMITSMU_11_0_7_ODCAP_FAN_ACOUSTIC_LIMITSMU_11_0_7_ODCAP_FAN_SPEED_MINSMU_11_0_7_ODCAP_TEMPERATURE_FANSMU_11_0_7_ODCAP_TEMPERATURE_SYSTEMSMU_11_0_7_ODCAP_MEMORY_TIMING_TUNESMU_11_0_7_ODCAP_FAN_ZERO_RPM_CONTROLSMU_11_0_7_ODCAP_AUTO_UV_ENGINESMU_11_0_7_ODCAP_AUTO_OC_ENGINESMU_11_0_7_ODCAP_AUTO_OC_MEMORYSMU_11_0_7_ODCAP_FAN_CURVESMU_11_0_ODCAP_AUTO_FAN_ACOUSTIC_LIMITSMU_11_0_7_ODCAP_POWER_MODESMU_11_0_7_ODCAP_COUNTSMU_11_0_7_ODSETTING_IDSMU_11_0_7_ODSETTING_GFXCLKFMAXSMU_11_0_7_ODSETTING_GFXCLKFMINSMU_11_0_7_ODSETTING_CUSTOM_GFX_VF_CURVE_ASMU_11_0_7_ODSETTING_CUSTOM_GFX_VF_CURVE_BSMU_11_0_7_ODSETTING_CUSTOM_GFX_VF_CURVE_CSMU_11_0_7_ODSETTING_CUSTOM_CURVE_VFT_FMINSMU_11_0_7_ODSETTING_UCLKFMINSMU_11_0_7_ODSETTING_UCLKFMAXSMU_11_0_7_ODSETTING_POWERPERCENTAGESMU_11_0_7_ODSETTING_FANRPMMINSMU_11_0_7_ODSETTING_FANRPMACOUSTICLIMITSMU_11_0_7_ODSETTING_FANTARGETTEMPERATURESMU_11_0_7_ODSETTING_OPERATINGTEMPMAXSMU_11_0_7_ODSETTING_ACTIMINGSMU_11_0_7_ODSETTING_FAN_ZERO_RPM_CONTROLSMU_11_0_7_ODSETTING_AUTOUVENGINESMU_11_0_7_ODSETTING_AUTOOCENGINESMU_11_0_7_ODSETTING_AUTOOCMEMORYSMU_11_0_7_ODSETTING_FAN_CURVE_TEMPERATURE_1SMU_11_0_7_ODSETTING_FAN_CURVE_SPEED_1SMU_11_0_7_ODSETTING_FAN_CURVE_TEMPERATURE_2SMU_11_0_7_ODSETTING_FAN_CURVE_SPEED_2SMU_11_0_7_ODSETTING_FAN_CURVE_TEMPERATURE_3SMU_11_0_7_ODSETTING_FAN_CURVE_SPEED_3SMU_11_0_7_ODSETTING_FAN_CURVE_TEMPERATURE_4SMU_11_0_7_ODSETTING_FAN_CURVE_SPEED_4SMU_11_0_7_ODSETTING_FAN_CURVE_TEMPERATURE_5SMU_11_0_7_ODSETTING_FAN_CURVE_SPEED_5SMU_11_0_7_ODSETTING_AUTO_FAN_ACOUSTIC_LIMITSMU_11_0_7_ODSETTING_POWER_MODESMU_11_0_7_ODSETTING_COUNTsmu_11_0_7_overdrive_tablepm_settingsmu_11_0_7_power_saving_clock_tablesmu_11_0_7_powerplay_tableDpmClock_tNumDcfClkDpmEnabledNumSocClkDpmEnabledNumFClkDpmEnabledNumMemClkDpmEnabledNumVClkDpmEnabledNumDClkDpmEnabledCLOCK_SMNCLKCLOCK_SOCCLKCLOCK_MP0CLKCLOCK_MP1CLKCLOCK_MP2CLKCLOCK_VCLKCLOCK_LCLKCLOCK_DCLKCLOCK_ACLKCLOCK_ISPCLKCLOCK_SHUBCLKCLOCK_DISPCLKCLOCK_DPPCLKCLOCK_DPREFCLKCLOCK_DCFCLKCLOCK_FCLKCLOCK_UMCCLKCLOCK_GFXCLKCLOCK_COUNTClockFrequencyAverageUvdActivityFanPwmStapmOriginalLimitLowFreqHighFreqWifiOneBand_tWifiBandEntryNumWifiBandEntryWifiBandEntryTable_tsmu_13_0_max_sustainable_clocksFEATURE_PWR_ALLFEATURE_PWR_S5FEATURE_PWR_BACOFEATURE_PWR_SOCFEATURE_PWR_GFXFEATURE_PWR_DOMAIN_COUNTAVFS_TEMP_COLDAVFS_TEMP_HOTAVFS_TEMP_COUNTAVFS_D_GAVFS_D_M_BAVFS_D_M_SAVFS_D_COUNTCalculateFoptPadding3Padding4FoptimalDcFoptimalAcTEMP_HOTSPOT_GTEMP_HOTSPOT_MTEMP_VR_UTDC_THROTTLER_USVI_PLANE_GFXSVI_PLANE_SOCSVI_PLANE_VMEMPSVI_PLANE_VDDIO_MEMSVI_PLANE_USVI_PLANE_COUNTPMFW_VOLT_PLANE_GFXPMFW_VOLT_PLANE_SOCPMFW_VOLT_PLANE_COUNTMEM_VENDOR_PLACEHOLDER0MEM_VENDOR_SAMSUNGMEM_VENDOR_INFINEONMEM_VENDOR_ELPIDAMEM_VENDOR_ETRONMEM_VENDOR_NANYAMEM_VENDOR_HYNIXMEM_VENDOR_MOSELMEM_VENDOR_WINBONDMEM_VENDOR_ESMTMEM_VENDOR_PLACEHOLDER1MEM_VENDOR_PLACEHOLDER2MEM_VENDOR_PLACEHOLDER3MEM_VENDOR_PLACEHOLDER4MEM_VENDOR_PLACEHOLDER5MEM_VENDOR_MICRONMEM_VENDOR_COUNTPP_GRTAVFS_HW_CPO_CTL_ZONE0PP_GRTAVFS_HW_CPO_CTL_ZONE1PP_GRTAVFS_HW_CPO_CTL_ZONE2PP_GRTAVFS_HW_CPO_CTL_ZONE3PP_GRTAVFS_HW_CPO_CTL_ZONE4PP_GRTAVFS_HW_CPO_EN_0_31_ZONE0PP_GRTAVFS_HW_CPO_EN_32_63_ZONE0PP_GRTAVFS_HW_CPO_EN_0_31_ZONE1PP_GRTAVFS_HW_CPO_EN_32_63_ZONE1PP_GRTAVFS_HW_CPO_EN_0_31_ZONE2PP_GRTAVFS_HW_CPO_EN_32_63_ZONE2PP_GRTAVFS_HW_CPO_EN_0_31_ZONE3PP_GRTAVFS_HW_CPO_EN_32_63_ZONE3PP_GRTAVFS_HW_CPO_EN_0_31_ZONE4PP_GRTAVFS_HW_CPO_EN_32_63_ZONE4PP_GRTAVFS_HW_ZONE0_VFPP_GRTAVFS_HW_ZONE1_VF1PP_GRTAVFS_HW_ZONE2_VF2PP_GRTAVFS_HW_ZONE3_VF3PP_GRTAVFS_HW_VOLTAGE_GBPP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE0PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE1PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE2PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE3PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE4PP_GRTAVFS_HW_RESERVED_0PP_GRTAVFS_HW_RESERVED_1PP_GRTAVFS_HW_RESERVED_2PP_GRTAVFS_HW_RESERVED_3PP_GRTAVFS_HW_RESERVED_4PP_GRTAVFS_HW_RESERVED_5PP_GRTAVFS_HW_RESERVED_6PP_GRTAVFS_HW_FUSE_COUNTPP_GRTAVFS_FW_COMMON_PPVMIN_Z1_HOT_T0PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_COLD_T0PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_HOT_T0PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_COLD_T0PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_HOT_T0PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_COLD_T0PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_HOT_T0PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_COLD_T0PP_GRTAVFS_FW_COMMON_SRAM_RM_Z0PP_GRTAVFS_FW_COMMON_SRAM_RM_Z1PP_GRTAVFS_FW_COMMON_SRAM_RM_Z2PP_GRTAVFS_FW_COMMON_SRAM_RM_Z3PP_GRTAVFS_FW_COMMON_SRAM_RM_Z4PP_GRTAVFS_FW_COMMON_FUSE_COUNTPP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_NEG_1PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_0PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_1PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_2PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_3PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_4PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_NEG_1PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_0PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_1PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_2PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_3PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_4PP_GRTAVFS_FW_SEP_FUSE_VF_NEG_1_FREQUENCYPP_GRTAVFS_FW_SEP_FUSE_VF4_FREQUENCYPP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_0PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_1PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_2PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_3PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4PP_GRTAVFS_FW_SEP_FUSE_COUNTOffsetMaxCurrentSviTelemetryScale_tFAN_MODE_AUTOFAN_MODE_MANUAL_LINEARFeatureCtrlMaskVoltageOffsetPerZoneBoundaryPptTdcAcousticTargetRpmThresholdAcousticLimitRpmThresholdOverDriveTableOverDriveTableExternal_tOverDriveLimits_tInitGfxclk_bypassInitSocclkInitMp0clkInitMpioclkInitSmnclkInitUcpclkInitCsrclkInitDprefclkInitDcfclkInitDtbclkInitDclkInitVclkInitUsbdfsclkInitMp1clkInitLclkInitBaco400clk_bypassInitBaco1200clk_bypassInitBaco700clk_bypassInitFclkInitGfxclk_clkbInitUclkDPMStateInitVcoFreqPll0InitVcoFreqPll1InitVcoFreqPll2InitVcoFreqPll3InitVcoFreqPll4InitVcoFreqPll5InitVcoFreqPll6InitGfxInitSocInitUBootValues_tTemperaturePwmLimitMinPwmLimitMaxSpare1AcousticTargetRpmThresholdMinAcousticTargetRpmThresholdMaxAcousticLimitRpmThresholdMinAcousticLimitRpmThresholdMaxPccLimitMinPccLimitMaxFanStopTempMinFanStopTempMaxFanStartTempMinFanStartTempMaxPowerMinPpt0MsgLimits_tBaseClockAcGameClockAcBoostClockAcBaseClockDcGameClockDcBoostClockDcDriverReportedClocks_tDcBtcGbScalarAvfsDcBtcParams_tAvfsTempVftFMinqVftqAvfsGb2MemoryTemperatureTypeMaskSmartShiftVersionSocketPowerLimitSmartShift2EnableLegacyPptLimitUseInputTelemetrySmartShiftMinReportedPptinDcsPaddingPptVrTdcLimitPlatformTdcLimitHwCtfTempLimitPaddingInfraFitControllerFailureRateLimitFitControllerGfxDutyCycleFitControllerSocDutyCycleFitControllerSocOffsetGfxApccPlusResidencyLimitUlvVoltageOffsetUlvVoltageOffsetUDeepUlvVoltageOffsetSocDefaultMaxVoltageBoostMaxVoltageVminTempHystersisVminTempThresholdVmin_Hot_T0Vmin_Cold_T0Vmin_Hot_EolVmin_Cold_EolVmin_Aging_OffsetSpare_Vmin_Plat_Offset_HotSpare_Vmin_Plat_Offset_ColdPerPartVminEnabledVmin_droopSpareVminFreqTableDppClkFreqTableDprefclkFreqTableDcfclkGfxclkSpareGfxclkFreqCapGfxclkFgfxoffExitImuGfxclkFgfxoffExitRlcGfxclkThrottleClockEnableGfxPowerStagesGpioGfxIdlePaddingSmsRepairWRCKClkDivEnSmsRepairWRCKClkDivValGfxOffEntryEarlyMGCGEnGfxOffEntryForceCGCGEnGfxOffEntryForceCGCGDelayEnGfxOffEntryForceCGCGDelayValGfxclkFreqGfxUlvGfxIdlePadding2GfxOffEntryHysteresisGfxoffSpareDfllBtcMasterScalerMDfllBtcMasterScalerBDfllBtcSlaveScalerMDfllBtcSlaveScalerBDfllPccAsWaitCtrlDfllPccAsStepCtrlDfllL2FrequencyBoostMDfllL2FrequencyBoostBGfxGpoSparePaddingDcsFoptEnabledDcsSpare2DcsFoptMDcsFoptBDcsSpareShadowFreqTableUclkUseStrobeModeOptimizationsMemVmempVoltageMemVddioVoltageFclkDpmUPstatesFclkDpmVddUFclkDpmUSpeedFclkDpmDisallowPstateFreqPaddingFclkFanGainPaddingMGpuAcousticLimitRpmThresholdTempInputSelectMaskFwCtfLimitIntakeTempEnableRPMIntakeTempOffsetTempIntakeTempReleaseTempIntakeTempHighIntakeAcousticLimitIntakeTempAcouticLimitReleaseRateFanAbnormalTempLimitOffsetFanStalledTriggerRpmFanAbnormalTriggerRpmCoeffFanAbnormalDetectionEnableFanIntakeSensorSupportFanIntakePaddingOverrideGfxAvfsFusesGfxAvfsPaddingL2HwRtAvfsFusesSeHwRtAvfsFusesCommonRtAvfsL2FwRtAvfsFusesSeFwRtAvfsFusesDroop_PWL_FDroop_PWL_aDroop_PWL_bDroop_PWL_cStatic_PWL_OffsetdGbV_dT_vmindGbV_dT_vmaxV2F_vmin_range_lowV2F_vmin_range_highV2F_vmax_range_lowV2F_vmax_range_highDcBtcGfxParamsGfxAvfsSpareOverrideSocAvfsFusesMinSocAvfsRevisionSocAvfsPaddingSocAvfsFuseOverrideDcBtcSocParamsSocAvfsSpareBootValuesDriverReportedClocksMsgLimitsOverDriveLimitsMinOverDriveLimitsBasicMaxTotalBoardPowerSupportTotalBoardPowerPaddingTotalIdleBoardPowerMTotalIdleBoardPowerBTotalBoardPowerMTotalBoardPowerBqFeffCoeffGameClockqFeffCoeffBaseClockqFeffCoeffBoostClockTemperatureLimit_HynixTemperatureLimit_MicronTemperatureFwCtfLimit_HynixTemperatureFwCtfLimit_MicronSkuTable_tVmempUlvPhaseSheddingMaskVddioUlvPhaseSheddingMaskSlaveAddrMappingVrPsiSupportPaddingPsiEnablePsi6SviTelemetryScaleVoltageTelemetryRatioDownSlewRateVrLedOffGpioFanOffGpioGfxVrPowerStageOffGpioUclkTrainingModeSpreadPercentGfxclkSpreadEnableDramWidthPostVoltageSetBacoDelayBacoEntryDelayFuseWritePowerMuxPresentFuseWritePaddingBoardSpareBoardTable_tSkuTableBoardTableAverageMemclkFrequencyPreDsAverageMemclkFrequencyPostDsPCIeBusydGPU_W_MAXAvgVoltageAvgCurrentVcn0ActivityPercentageVcn1ActivityPercentageAverageTotalBoardPowerAvgTemperatureAvgTemperatureFanIntakeAvgFanPwmAvgFanRpmVmaxThrottlingPercentageAvgApuSocketPowerAverageUclkActivity_MAXPublicSerialNumberLowerPublicSerialNumberUpperSMU_13_0_0_ODFEATURE_CAPSMU_13_0_0_ODCAP_GFXCLK_LIMITSSMU_13_0_0_ODCAP_UCLK_LIMITSSMU_13_0_0_ODCAP_POWER_LIMITSMU_13_0_0_ODCAP_FAN_ACOUSTIC_LIMITSMU_13_0_0_ODCAP_FAN_SPEED_MINSMU_13_0_0_ODCAP_TEMPERATURE_FANSMU_13_0_0_ODCAP_TEMPERATURE_SYSTEMSMU_13_0_0_ODCAP_MEMORY_TIMING_TUNESMU_13_0_0_ODCAP_FAN_ZERO_RPM_CONTROLSMU_13_0_0_ODCAP_AUTO_UV_ENGINESMU_13_0_0_ODCAP_AUTO_OC_ENGINESMU_13_0_0_ODCAP_AUTO_OC_MEMORYSMU_13_0_0_ODCAP_FAN_CURVESMU_13_0_0_ODCAP_AUTO_FAN_ACOUSTIC_LIMITSMU_13_0_0_ODCAP_POWER_MODESMU_13_0_0_ODCAP_PER_ZONE_GFX_VOLTAGE_OFFSETSMU_13_0_0_ODCAP_COUNTSMU_13_0_0_ODSETTING_IDSMU_13_0_0_ODSETTING_GFXCLKFMAXSMU_13_0_0_ODSETTING_GFXCLKFMINSMU_13_0_0_ODSETTING_UCLKFMINSMU_13_0_0_ODSETTING_UCLKFMAXSMU_13_0_0_ODSETTING_POWERPERCENTAGESMU_13_0_0_ODSETTING_FANRPMMINSMU_13_0_0_ODSETTING_FANRPMACOUSTICLIMITSMU_13_0_0_ODSETTING_FANTARGETTEMPERATURESMU_13_0_0_ODSETTING_OPERATINGTEMPMAXSMU_13_0_0_ODSETTING_ACTIMINGSMU_13_0_0_ODSETTING_FAN_ZERO_RPM_CONTROLSMU_13_0_0_ODSETTING_AUTOUVENGINESMU_13_0_0_ODSETTING_AUTOOCENGINESMU_13_0_0_ODSETTING_AUTOOCMEMORYSMU_13_0_0_ODSETTING_FAN_CURVE_TEMPERATURE_1SMU_13_0_0_ODSETTING_FAN_CURVE_SPEED_1SMU_13_0_0_ODSETTING_FAN_CURVE_TEMPERATURE_2SMU_13_0_0_ODSETTING_FAN_CURVE_SPEED_2SMU_13_0_0_ODSETTING_FAN_CURVE_TEMPERATURE_3SMU_13_0_0_ODSETTING_FAN_CURVE_SPEED_3SMU_13_0_0_ODSETTING_FAN_CURVE_TEMPERATURE_4SMU_13_0_0_ODSETTING_FAN_CURVE_SPEED_4SMU_13_0_0_ODSETTING_FAN_CURVE_TEMPERATURE_5SMU_13_0_0_ODSETTING_FAN_CURVE_SPEED_5SMU_13_0_0_ODSETTING_AUTO_FAN_ACOUSTIC_LIMITSMU_13_0_0_ODSETTING_POWER_MODESMU_13_0_0_ODSETTING_PER_ZONE_GFX_VOLTAGE_OFFSET_POINT_1SMU_13_0_0_ODSETTING_PER_ZONE_GFX_VOLTAGE_OFFSET_POINT_2SMU_13_0_0_ODSETTING_PER_ZONE_GFX_VOLTAGE_OFFSET_POINT_3SMU_13_0_0_ODSETTING_PER_ZONE_GFX_VOLTAGE_OFFSET_POINT_4SMU_13_0_0_ODSETTING_PER_ZONE_GFX_VOLTAGE_OFFSET_POINT_5SMU_13_0_0_ODSETTING_PER_ZONE_GFX_VOLTAGE_OFFSET_POINT_6SMU_13_0_0_ODSETTING_COUNTsmu_13_0_0_overdrive_tablesmu_13_0_0_powerplay_tableatom_smc_dpm_info_table_13_0_0OverDriveLimitsAdvancedMaxFclkSpreadPaddingSMU_13_0_7_ODFEATURE_CAPSMU_13_0_7_ODCAP_GFXCLK_LIMITSSMU_13_0_7_ODCAP_UCLK_LIMITSSMU_13_0_7_ODCAP_POWER_LIMITSMU_13_0_7_ODCAP_FAN_ACOUSTIC_LIMITSMU_13_0_7_ODCAP_FAN_SPEED_MINSMU_13_0_7_ODCAP_TEMPERATURE_FANSMU_13_0_7_ODCAP_TEMPERATURE_SYSTEMSMU_13_0_7_ODCAP_MEMORY_TIMING_TUNESMU_13_0_7_ODCAP_FAN_ZERO_RPM_CONTROLSMU_13_0_7_ODCAP_AUTO_UV_ENGINESMU_13_0_7_ODCAP_AUTO_OC_ENGINESMU_13_0_7_ODCAP_AUTO_OC_MEMORYSMU_13_0_7_ODCAP_FAN_CURVESMU_13_0_7_ODCAP_AUTO_FAN_ACOUSTIC_LIMITSMU_13_0_7_ODCAP_POWER_MODESMU_13_0_7_ODCAP_PER_ZONE_GFX_VOLTAGE_OFFSETSMU_13_0_7_ODCAP_COUNTSMU_13_0_7_ODSETTING_IDSMU_13_0_7_ODSETTING_GFXCLKFMAXSMU_13_0_7_ODSETTING_GFXCLKFMINSMU_13_0_7_ODSETTING_UCLKFMINSMU_13_0_7_ODSETTING_UCLKFMAXSMU_13_0_7_ODSETTING_POWERPERCENTAGESMU_13_0_7_ODSETTING_FANRPMMINSMU_13_0_7_ODSETTING_FANRPMACOUSTICLIMITSMU_13_0_7_ODSETTING_FANTARGETTEMPERATURESMU_13_0_7_ODSETTING_OPERATINGTEMPMAXSMU_13_0_7_ODSETTING_ACTIMINGSMU_13_0_7_ODSETTING_FAN_ZERO_RPM_CONTROLSMU_13_0_7_ODSETTING_AUTOUVENGINESMU_13_0_7_ODSETTING_AUTOOCENGINESMU_13_0_7_ODSETTING_AUTOOCMEMORYSMU_13_0_7_ODSETTING_FAN_CURVE_TEMPERATURE_1SMU_13_0_7_ODSETTING_FAN_CURVE_SPEED_1SMU_13_0_7_ODSETTING_FAN_CURVE_TEMPERATURE_2SMU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dgpu_display_crtc_idx_to_irq_typepage_flip_flagsamdgpu_display_crtc_page_flip_targetamdgpu_display_crtc_scaling_mode_fixupamdgpu_display_crtc_set_configuse_auxamdgpu_display_ddc_probeamdgpu_display_flip_callbackamdgpu_display_flip_work_funcrfbamdgpu_display_framebuffer_initamdgpu_display_get_crtc_scanoutposamdgpu_display_hotplug_work_funcamdgpu_display_modeset_create_propsamdgpu_display_print_display_setupamdgpu_display_resume_helperamdgpu_display_supported_domainsamdgpu_display_suspend_helperamdgpu_display_unpin_work_funcamdgpu_display_update_priorityamdgpu_display_user_framebuffer_createblock_size_log2amdgpu_display_verify_planeamdgpu_display_verify_sizesamdgpu_dm_atomic_checkamdgpu_dm_atomic_commit_tailamdgpu_dm_atomic_setup_commithda_kdevamdgpu_dm_audio_component_bindamdgpu_dm_audio_component_get_eldamdgpu_dm_audio_component_unbindamdgpu_dm_audio_eld_notifyamdgpu_dm_backlight_get_brightnessamdgpu_dm_backlight_set_levelamdgpu_dm_backlight_update_statusamdgpu_dm_commit_audioamdgpu_dm_commit_cursorspcrtcwait_for_vblankamdgpu_dm_commit_planesamdgpu_dm_commit_streamsamdgpu_dm_connector_add_common_modesamdgpu_dm_connector_atomic_checkamdgpu_dm_connector_atomic_duplicate_stateamdgpu_dm_connector_atomic_get_propertyamdgpu_dm_connector_atomic_set_propertyamdgpu_dm_connector_destroyamdgpu_dm_connector_detectamdgpu_dm_connector_funcs_forceamdgpu_dm_connector_funcs_resetamdgpu_dm_connector_get_modesaencoderamdgpu_dm_connector_initamdgpu_dm_connector_init_helperamdgpu_dm_connector_late_registeramdgpu_dm_connector_mode_validamdgpu_dm_connector_to_encoderamdgpu_dm_connector_unregisteramdgpu_dm_create_common_modeamdgpu_dm_dmub_reg_readamdgpu_dm_dmub_reg_writeamdgpu_dm_early_finiamdgpu_dm_find_first_crtc_matching_connectoramdgpu_dm_finiamdgpu_dm_get_encoder_crtc_maskamdgpu_dm_i2c_funcamdgpu_dm_i2c_xferamdgpu_dm_initamdgpu_dm_initialize_drm_deviceamdgpu_dm_link_setup_psramdgpu_dm_mode_config_initamdgpu_dm_process_dmub_aux_transfer_syncamdgpu_dm_process_dmub_set_config_syncamdgpu_dm_psr_disableamdgpu_dm_psr_disable_allamdgpu_dm_psr_enableamdgpu_dm_set_psr_capsamdgpu_dm_trigger_timing_syncamdgpu_dm_update_backlight_capsamdgpu_dm_update_connector_after_detectamdgpu_dm_update_freesync_capsamdgpu_dma_buf_attachamdgpu_dma_buf_begin_cpu_accessamdgpu_dma_buf_detachamdgpu_dma_buf_mapamdgpu_dma_buf_move_notifyamdgpu_dma_buf_pinamdgpu_dma_buf_unmapamdgpu_dma_buf_unpinamdgpu_dmabuf_is_xgmi_accessibleamdgpu_doorbell_create_kernel_doorbellsamdgpu_doorbell_finidb_bodb_sizeamdgpu_doorbell_index_on_baramdgpu_doorbell_initamdgpu_eeprom_readamdgpu_eeprom_writeamdgpu_eeprom_xferamdgpu_evict_gtt_fops_openamdgpu_evict_vram_fops_openamdgpu_fence_count_emittedamdgpu_fence_driver_clear_job_fencesamdgpu_fence_driver_force_completionamdgpu_fence_driver_hw_finiamdgpu_fence_driver_hw_initamdgpu_fence_driver_init_ringamdgpu_fence_driver_isr_toggleamdgpu_fence_driver_set_erroramdgpu_fence_driver_start_ringamdgpu_fence_driver_sw_finiamdgpu_fence_driver_sw_initamdgpu_fence_emitamdgpu_fence_emit_pollingamdgpu_fence_enable_signalingamdgpu_fence_fallbackamdgpu_fence_freeamdgpu_fence_get_driver_nameamdgpu_fence_get_timeline_nameamdgpu_fence_last_unsignaled_time_usamdgpu_fence_need_ring_interrupt_restoreamdgpu_fence_processamdgpu_fence_releaseamdgpu_fence_slab_finiamdgpu_fence_slab_initamdgpu_fence_update_start_timestampamdgpu_fence_wait_emptywait_seqamdgpu_fence_wait_pollingamdgpu_free_static_csaamdgpu_gem_prime_exportamdgpu_gem_prime_importamdgpu_get_xgmi_hiveamdgpu_gmc_agp_addramdgpu_gmc_agp_locationamdgpu_gmc_allocate_vm_inv_engamdgpu_gmc_filter_faultsamdgpu_gmc_filter_faults_removeamdgpu_gmc_flush_gpu_tlbamdgpu_gmc_flush_gpu_tlb_pasidgart_placementamdgpu_gmc_gart_locationamdgpu_gmc_get_pde_for_boamdgpu_gmc_get_vbios_allocationsamdgpu_gmc_init_pdb0amdgpu_gmc_noretry_setamdgpu_gmc_pd_addramdgpu_gmc_pdb0_allocamdgpu_gmc_ras_finiamdgpu_gmc_ras_late_initamdgpu_gmc_ras_sw_initamdgpu_gmc_set_agp_defaultcpu_pt_addrgpu_page_idxamdgpu_gmc_set_pte_pdeamdgpu_gmc_set_vm_fault_masksamdgpu_gmc_sysfs_finiamdgpu_gmc_sysfs_initamdgpu_gmc_sysvm_locationamdgpu_gmc_tmz_setamdgpu_gmc_vram_checkingamdgpu_gmc_vram_cpu_paamdgpu_gmc_vram_locationamdgpu_gmc_vram_mc2paamdgpu_gmc_vram_paamdgpu_gtt_mgr_compatibleamdgpu_gtt_mgr_debugamdgpu_gtt_mgr_delamdgpu_gtt_mgr_finiamdgpu_gtt_mgr_has_gart_addramdgpu_gtt_mgr_initamdgpu_gtt_mgr_intersectsamdgpu_gtt_mgr_newamdgpu_gtt_mgr_recoveramdgpu_has_atpxamdgpu_has_atpx_dgpu_power_cntlamdgpu_irq_add_domainamdgpu_irq_add_idamdgpu_irq_create_mappingamdgpu_irq_delegateamdgpu_irq_disable_allamdgpu_irq_dispatchamdgpu_irq_enabledamdgpu_irq_fini_hwamdgpu_irq_fini_swamdgpu_irq_getamdgpu_irq_gpu_reset_resume_helperamdgpu_irq_handle_ih1amdgpu_irq_handle_ih2amdgpu_irq_handle_ih_softamdgpu_irq_handleramdgpu_irq_initamdgpu_irq_maskamdgpu_irq_putamdgpu_irq_remove_domainamdgpu_irq_unmaskamdgpu_irq_updateamdgpu_irqdomain_mapamdgpu_is_atpx_hybridamdgpu_job_fence_enable_signalingamdgpu_job_fence_freeamdgpu_job_fence_get_timeline_nameamdgpu_job_fence_releaseamdgp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